Hello,
This is a very hard question to answer some one asked me ...
we all know that Intel CPU has PCI-e Lanes ...
some 16 , some 40 some 32 lanes etc ...
The Question is :
Can the CPU Access the Data simultaneously from all lanes in both ways send/receive ? and is there any bottleneck inside the cpu itself similar to the Chip-set DMI link ?
We all know that Z170 chipset can offer 20 PCIe 3.0 lanes ...but there is a bottleneck that stops it from reaching the full bandwidth of those 20 lanes , that is the DMI link between the CPU and the chipset which is equivalent to 4 PCIe 3.0 lanes only (DMI 3.0 = 4000MB/s).
My question is : what about the CPU itself internally ? does it also have bandwidth bottleneck when it comes to accessing Data from the PCIe lanes ? and how much is that bottleneck ?
This is a very hard question to answer some one asked me ...
we all know that Intel CPU has PCI-e Lanes ...
some 16 , some 40 some 32 lanes etc ...
The Question is :
Can the CPU Access the Data simultaneously from all lanes in both ways send/receive ? and is there any bottleneck inside the cpu itself similar to the Chip-set DMI link ?
We all know that Z170 chipset can offer 20 PCIe 3.0 lanes ...but there is a bottleneck that stops it from reaching the full bandwidth of those 20 lanes , that is the DMI link between the CPU and the chipset which is equivalent to 4 PCIe 3.0 lanes only (DMI 3.0 = 4000MB/s).
My question is : what about the CPU itself internally ? does it also have bandwidth bottleneck when it comes to accessing Data from the PCIe lanes ? and how much is that bottleneck ?
Facebook
Twitter
Instagram