gokussj9 :
Hi,
I have been reading DRAM column read protocol which is basically defined by three timing
paremeters (1) tcas (2) tccd - column to column delay and (3) tburst- data burst duration
I am not able to understand the timing parameters (2) and (3). The text which I am reading
says that tccd is DRAM internal burst length and duration of the data burst on data bus is tburst.
Can anybody explain me these two timing parameters and why they are named so?
Thanks.
DDRx SDRAM uses data bursts to improve data throughput. When a memory controller issues a read operation, the DRAM ICs return the requested column address as well as several adjacent addresses. This is called the prefetch depth. DDR SDRAM has a prefetch buffer of 2n, which means it returns two words for each read operation. DDR2 SDRAM has a prefetch buffer of 4n, which means that it returns four words for every read operation. DDR3 SDRAM and DDR4 SDRAM have prefetch buffers of 8n (although 4n can be done by enabling burst chop), so they return eight words for every read operation. The order words that are returned (burst order) in DDR3 SDRAM depend on the lower three bits of the column address.
000 = 0,1,2,3,4,5,6,7
001 = 1,2,3,0,5,6,7,4
010 = 2,3,0,1,6,7,4,5
011 = 3,0,1,2,7,4,5,6
100 = 4,5,6,7,0,1,2,3
101 = 5,6,7,4,1,2,3,0
110 = 6,7,4,5,2,3,0,1
111 = 7,4,5,6,3,0,1,2
From this it becomes apparent that DDR3 SDRAM pages are organized into eight word chunks and there are eight possible column addresses that can be used to read this chunk in eight different orders.
When a bank receives a read operation, it loads the respective chunk from the sense amplifiers into the prefetch buffer in the order indicated by the three LSBs of the column address. This operation takes Tcl cycles to complete (column latency) after which the burst period begins. Data from the prefetch buffer is then strobed onto the bus every half cycle until the prefetch buffer is empty.
For example, DDR3-1600 with CL9 has a clock period of 1.25 nanoseconds. If a read command is issued at t = 0, the first word of the burst will be strobed onto the IO bus at t = (9 * 1.25ns) = 11.25ns. A subsequent word will be strobed every 625ps until all 8 words have been strobed; this occurs at t = (9 * 1.25ns) + (7 * 625ps) = 15.625 ns. This period is the sum of Tcl + Tburst where Tcl is the time between the read command and the first word of the burst and Tburst is the period of the burst.
Tccd is the minimum amount of time between column operations. Subsequent reads to the same bank must be at least Tburst ns (or equivalent cycles) apart because it takes at least Tburst to transfer the burst from the prefetch buffer to the IO bus. On DDR3, Tburst is four cycles (two transfers per cycle * four cycles = eight transfers); however, in some architectures Tccd may be greater than Tburst; it cannot however be less than Tburst.
If read commands are issued faster than Tccd, then some of the data from the earlier read operation will be overwritten by data from the later read operation as it proceeds through the buffers and the memory controller will lose track of what data belongs to what address.
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