News Epyc AMD Milan-X Delidding Reveals a Surprising Lack of Separate Silicon Shims

[Admin]

Delidding of this powerful server chip reveals that the multiple or U-shaped silicon shims shown in chip package diagrams weren't used in the shipping processors.

Epyc AMD Milan-X Delidding Reveals a Surprising Lack of Separate Silicon Shims : Read more

 

[InvalidError]

I'd imagine making a U-shaped shim that fits snugly around the cache chip would be a quite substantial manufacturing challenge.

 

[drajitsh]

Really impressive detective work. Also thanks to Tom's for reporting

 

[digitalgriffin]

I'd imagine making a U-shaped shim that fits snugly around the cache chip would be a quite substantial manufacturing challenge.

I was thinking the same thing. To be honest I'm surprised the cache wasn't on the bottom of chip on the 5800X3D. The side with the most energy dissipation/density should be side up to the heat sink.

 

[InvalidError]

I was thinking the same thing. To be honest I'm surprised the cache wasn't on the bottom of chip on the 5800X3D. The side with the most energy dissipation/density should be side up to the heat sink.

Putting the cache at the bottom would cause its own lot of problems with passing 100+A through the extra layer, along with all of the high-speed signals. Adding it on top has much fewer potential points of failure at the expense of slightly worse thermal performance.

One way to make the top slab look monolithic at a glance but actually be a separate piece to save 7nm silicon would be to etch or machine a pocket in the slab for the cache die.

 

[escksu]

I was thinking the same thing. To be honest I'm surprised the cache wasn't on the bottom of chip on the 5800X3D. The side with the most energy dissipation/density should be side up to the heat sink.

AFAIK, Zen3 chiplets have their circuits facing "up" instead of "down" (not a flipchip design). these chiplets are using TSV to connect the chiplets to the substrate. So, what this means is that those contact bumps on the chiplets are at the bottom.

So, it is not possible to put the cache at the bottom. AMD is trying to minimise changes to the die, so the easiest and most cost effective way is to simply place the cache die on top of the chiplet.

 

[InvalidError]

AFAIK, Zen3 chiplets have their circuits facing "up" instead of "down" (not a flipchip design). these chiplets are using TSV to connect the chiplets to the substrate.

AMD's description of the cache chip attachment process contradicts that: it says the back of the CCDs needs to be etched away to expose the TSVs to which the cache chips will be attached, which means the cache chips are the ones attached to the back of the CCDs through the CCDs' TSVs which are still present but hidden and not doing anything on non-3D chiplets.