Everspin Rolls Out Non-Volatile Replacement Option for DRAM

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Before you all start posting about how 'useless' an 8MB chip is...

My First PC had 64KB (yes, that is a 'K') memory and a 5MB hard drive in full height 5 1/4" format.
Darn thing cost a month' salary too.

Anyway, this type chip technology has obviously some ways to go to find it's way into regular PCs, but there are all sorts of intermediate applications in the low power segment of the market that I can see for them in the very near future.

 
And also, we're talking about a brand-new memory system that has relatively little limit on how much it can be improved (other than financial investments). Flash and DRAM had a obviously huge headstart, but both are reaching a limit on how much they can improved before you have to make sacrifices.

Flash, like the CPUs, is hitting a limit on how far silicon can go. DRAM is also increasingly having less of its silicon dies reserved for actual memory storage and more for other functions such as interconnects.
 
I would assume that a comparison to 25nm (or less) NAND would be a better comparison than Intel's 22nm process for tri-gate transistors...
 
I never fully understood the word "torque" when it was used with automobiles, and I certainly don't now, when it is used with DRAM.

Someone explain it to me like you would an 8-year-old.
 
Cleary this tech needs a lot of investment in shrinking the process. It's great that they actually build that chip, even if it's only 8MB. Because now it's a real deal, not some far far away concept. This will lure some investors for sure. And with Dram prices on all the time low, everyone could afford lighting-fast:) RAM drive

good luck guys, keep this up, can't wait for mainstream version!
 
[citation][nom]merikafyeah[/nom]I never fully understood the word "torque" when it was used with automobiles, and I certainly don't now, when it is used with DRAM. Someone explain it to me like you would an 8-year-old.[/citation]
I honestly have no idea how they mean torque in this context, but torque is a rotational force. If you have a long, 'I' shaped bar, and you use one end to stop it from moving, and you use a machine to turn the other end, you are applying a torque. It doesn't always sound all that inviting, I mean, why not just call it a force? Well it is different than a regular force because things react differently to torque (there are whole suspension systems in cars that use torque). In the end, though, it is just another force.
 
[citation][nom]erraticfocus[/nom]Hey Intel, get in there with some investment monies![/citation]

Intel: Nope, too busy trying to beat down ARM and delivering the finishing blows to AMD.
 
[citation][nom]ojas[/nom]I would assume that a comparison to 25nm (or less) NAND would be a better comparison than Intel's 22nm process for tri-gate transistors...[/citation]

Still, any silicon process lower than 40nm is hitting the limits of physics.
 
MRAM is a definite possibility for SSD technology's future. It has everything that you would be looking for in the next chip technology.

But I still question its use as system memory as opposed to system storage. I get the functional use - not losing stuff in the memory when the system looses power, whether by power outage or shutdown. But I still think the focus would be better applied to improved read/write performance between the memory and the storage device. If the idea is for all the information to eventually be placed on the storage device, it seems a little strange to me to make memory into a pre-storage device to write to a primary storage device. I only mention this all because a similar story a few days ago was walking about memory chips that could story data for years after loss of power.
 
holy crap this is awesome!!!!!
If they can get density up a bit then we could see phones and tablets that take 0 power on active standby. It would be a litteral suspend to ram every time the ram is not being accessed! That would be HUGE in any application that requires a battery. But the obvious problems are cost and density. Phones (especially Androids) really need 2 GB of ram to properly multi-task, and 2GB of 8MB chips is simply going to take way too much space. Similarly, tablets will soon be shipping with 4-8GB of ram as it becomes a cheap point of comparison to sell devices, and 8GB of 8MB chips is going to take a crap load of space.

But if they can manage to up that density quickly, it could be revolutionary for standby battery life. In the mean time this is going to be perfect for low memory ARM devices like kitchen appliances, HVAC, and other more industrial uses.
 
[citation][nom]drosencraft[/nom]MRAM is a definite possibility for SSD technology's future. It has everything that you would be looking for in the next chip technology. But I still question its use as system memory as opposed to system storage. I get the functional use - not losing stuff in the memory when the system looses power, whether by power outage or shutdown. But I still think the focus would be better applied to improved read/write performance between the memory and the storage device. If the idea is for all the information to eventually be placed on the storage device, it seems a little strange to me to make memory into a pre-storage device to write to a primary storage device. I only mention this all because a similar story a few days ago was walking about memory chips that could story data for years after loss of power.[/citation]
not likely any good for long term storage solutions. We are looking at 1TB 'mainstream', and 2TB enthusiast SSDs in 2013. While this tech would have a much faster read/write than current SSD tech, it would be far too expensive and small to compete. At 8MB chips we are talking about 125,000 individual chips to populate a 1TB SSD, compared to the 16 chips used in today's flash memory designs, or 8 used in near-future designs. It dosn't matter how cheap they make each individual chip, even if they quadrupled chip density they would still not be able to approach the cost and space requirements for SSD use any time soon. It would be much more likely to be used as a RAM replacement.
 
[citation][nom]merikafyeah[/nom]I never fully understood the word "torque" when it was used with automobiles, and I certainly don't now, when it is used with DRAM. Someone explain it to me like you would an 8-year-old.[/citation]
I've no idea what it's meant by in this context.

As far as torque in a car goes, it's pretty easy to understand. It's rotational force. The force at the edge of the circle is multiplied by how far it is from the center.

Think of doing a curl with a 10lbs weight. Easy enough, right? Now try lifting the weight while keeping your elbow straight. All of the sudden that 10lbs weight seems a lot heavier! Well, the length of your full arm is about twice what you bend when you curl, so you roughly doubled the torque needed.

T=rF
Torque = radius * Force

On a car, you could (theoretically) measure the torque your wheels (axle, really) have. Since you can measure the radius of your tires, you now know how much force is being applied to the ground. Since we know Force = Mass * Acceleration, and we can find the weight of the car, we can now calculate the car's acceleration.

I say you could do this calculation theoretically because things are never ideal in the real world. First and foremost, engines don't put out a flat level of torque. They are more (and less) efficient depending on how fast they're reving, how much gas is pumped into the combustion chamber, etc. Inertia and friction are also big factors too.

Hope my inner physics nerd has helped a little bit.
 
[citation][nom]A Bad Day[/nom]DRAM is also increasingly having less of its silicon dies reserved for actual memory storage and more for other functions such as interconnects.[/citation]
No matter what type of memory technology is used, all need some form of addressing and sensing/writing grid to access individual storage cells so the amount of space dedicated to that is intrinsically tied to chip capacity. The size of address decoders and data (de)multiplexers are also intrinsically linked to chip capacities so there is no miracle to reduce the amount of space dedicated to those structures regardless of storage technology either.

The biggest bottlenecks with DRAM are the sense amplifiers and destructive reading: as cells become smaller, their capacitance goes down and the sense amplifiers have to become increasingly sensitive. To cut down on noise and parasitic capacitance on the sense lines, the number of rows connected to each sense amplifier has to be cut back and this means more sense amplifiers. Since those sense amplifiers are analog devices, they consume lots of power and silicon space compared to other structures which are either passive or simple CMOS logic.

Flash is also expected to run into bottlenecks from sense amplifiers in the not-so-distant-future but isn't as adversely affected by it since reading flash is non-destructive so amplifiers can take however long they need for sense voltage to stabilize, unlike DRAM where reading connects the cell capacitor to the precharged sense line and amplifiers have to detect the pulse before the charge disperses and data is lost, hence the need to "close" (rewrite) rows before accessing another.

I would not be surprised if MRAM ran into similar sense challenges as it evolves from 180nm niche-market to a potential DRAM replacement candidate since sensing on MRAM is still going to be an analog function.
 
Here's my attempt to explain the 'torque' bit - apologies in advance if it's at the wrong level. I work in the applied physics field involving spin torque (spintronics) and I have an enthusiast's basic knowledge of computer tech, but those two aspects are quite far apart in my head.

The torque being referred to is a magnetic torque - when an electrical current passes through a magnetic material, it gets 'spin-polarised'. You need to look into the physics of electrons a bit to understand that, but basically it means that a current coming out of a thin film magnet and into another thin film magnet exerts a magnetic torque on the second thin film.

As in magnetic hard drives, this type of storage is based on measuring the electrical resistance of one bit of storage, and the way that is done is by changing the direction that the magnetism of two layers points. If they point in the same direction, it is a low resistance state. Conversely, opposite directions mean high resistance - those are your 0 and 1 states right there.

The trick is how to change the orientation from 1 to 0 as you need for writing. You can use a magnetic field from outside, but that isn't too efficient and risks you switching the orientation of other bits than just the one you want. However, with this magnetic (or spin) torque, passing a current directly through the first magnetic layer lets you change the magnetic orientation of the second layer without a magnetic field at all. This won't affect any other bits around the one you're changing, and the smaller you make the bits, the less power this whole process takes.

FWIW, this is the WikiPedia article on spin-transfer torque, though it's pretty technical. http://en.wikipedia.org/wiki/Spin-transfer_torque

For me this is quite exciting - as the article says, it has been a decade or so since this type of storage was first promised. It's always good as an experimental research physicist to point to some piece of commercial tech making some company billions and say 'that's why you should continue to fund my research'.
 
[citation][nom]merikafyeah[/nom]I never fully understood the word "torque" when it was used with automobiles, and I certainly don't now, when it is used with DRAM. Someone explain it to me like you would an 8-year-old.[/citation]

the amount of force/effort it takes to make something go ( at a certain speed )
 
This has a potential to unify RAM and storage. One would simply have a computer with e.g. 128 GB of this and could configure e.g. 8 GB as operational memory and the rest as storage. Would be awesome for laptops/tablets.
 
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