News Evidence mounts that TSMC won't adopt next-gen EUV chipmaking tools until 1nm debuts in the 2030 timeframe

[Admin]

Fab toolmaker tells DigiTimes that TSMC will likely adopt High-NA at 1nm.

Evidence mounts that TSMC won't adopt next-gen EUV chipmaking tools until 1nm debuts in the 2030 timeframe : Read more

 

[The Historical Fidelity]

It just seems that a 5nm decrease in feature size capability is not worth the cost increase of the NA tool investment until it’s absolutely necessary. Which btw, NA EUV is kind of in the same ballpark as immersion lithography for DUV in that dry DUV has a single pattern feature size limit of 65nm and immersion DUV of 45nm which is a similar reduction scale as EUV 13nm to NA 8nm.

 

[jkflipflop98]

Depends on how many wafers you're making. The reduction in process steps is well worth it. Higher overall throughput and less impact to yields make this a no-brainer.

 

[The Historical Fidelity]

Depends on how many wafers you're making. The reduction in process steps is well worth it. Higher overall throughput and less impact to yields make this a no-brainer.

It’s TSMC so a lot of wafers and they know better than anyone whether it makes sense to double pattern vs invest in $500,000,000 tools. They chose double pattern for a reason.

 

[kjfatl]

This so reminds me of what Intel did about 10 years ago when they decided to due multiple patterning instead of investing in EUV. It took them from the undisputed #1 player in the market to #3. The expected path for TSMC would be to set up at least one fab with high NA EUV equipment so they can continue to develop their processes and go into high volume production on a few bleeding edge products. It looks like they have decided to hand the torch back to Intel.

 

[zodiacfml]

wow. If TSMC does not buy more NA EUV than Intel then all these years of Intel decline was intentional! Intel is taking the cutting edge semicon back. I could smell this from years ago! It is not like Intel could get behind TSMC as there were no signs of Intel mistakes or miss steps. the truth is, process node superiority is just buying the latest ASML equipment and hope you have volumes to pay for it.

 

[The Historical Fidelity]

wow. If TSMC does not buy more NA EUV than Intel then all these years of Intel decline was intentional! Intel is taking the cutting edge semicon back. I could smell this from years ago! It is not like Intel could get behind TSMC as there were no signs of Intel mistakes or miss steps. the truth is, process node superiority is just buying the latest ASML equipment and hope you have volumes to pay for it.

More like Intel knows that their processes are not on par with TSMC efficiency wise so they must utilize every advantage they can to control transistor leakage.

 

[The Historical Fidelity]

This so reminds me of what Intel did about 10 years ago when they decided to due multiple patterning instead of investing in EUV. It took them from the undisputed #1 player in the market to #3. The expected path for TSMC would be to set up at least one fab with high NA EUV equipment so they can continue to develop their processes and go into high volume production on a few bleeding edge products. It looks like they have decided to hand the torch back to Intel.

It’s apples to oranges, going from minimum feature sizes of 45nm with single pattern immersion DUV to 13nm single pattern EUV is much greater than from EUV 13nm to 8nm single pattern High NA EUV. IE Intel chose not to upgrade resolution by 3.5x vs TSMC choosing to not upgrade resolution by 0.6x. It won’t be anything that greatly affects TSMC’s leadership.

 

[phead128]

wow. If TSMC does not buy more NA EUV than Intel then all these years of Intel decline was intentional! Intel is taking the cutting edge semicon back. I could smell this from years ago! It is not like Intel could get behind TSMC as there were no signs of Intel mistakes or miss steps. the truth is, process node superiority is just buying the latest ASML equipment and hope you have volumes to pay for it.

They all have access to the same ASML EUV equipment, just TSMC is superior at systems integration and efficiency, so they can secure the volume orders from Apple. Intel is inferior in efficiency and yield, even with the same EUV tools, they can't get good cost-per-unit yields to compete with TSMC. They hope to compensate their weakness with more accurate overlays to improve performance, doesn't mean their cost efficiency will be the same.