I understand their hesitancy.
These chips today are extremely complex beasts as they try to exploit every nook and cranny for an extra bit of performance. And to explain these things to the level of detail that people are satisfied there are no longer hidden snags, would require bringing the audience to the level where they might have been part of the design team.
And not everyone who just loves to complain or start conspirational rumors will want to or be able to get there.
The logic for mixed 4 and 4c cores in TDP limited designs isn't that different from choice for the Ryzen 9 7950X3D to use a mix of CCDs. By the time you've exhausted the heat budget all the non-V-cache cores in the "fast" CCD, the fact that the cores in the V-cache CCD won't be able to reach non-cache peaks is no longer relevant, because with all cores active, everbody will have to take fewer Watts from the power faucet and reduce clocks anyway. It should work out to a very small clock disadvantage overall at 16 fully active cores.
Here with ~15 Watt total power budgets it's somewhat similar: when say in a 2(4)+6(4C) setup the 3rd core get loaded, the faster cores may have to clock down anyway to reduce their part of the total to a point where they are running at very similar clocks to what the 4C cores can sustain as max speeds. The extra dark silicon area that the high-frequency cores need for heat dissipation at their top frequencies doesn't deliver any benefit when the heat doesn't peak the same on the C-cores. Apart from the cache sizes (which probably still differ), there should be no measurable impact on performance, just more dies per wafer.
Of course the optimal relationship between 4 and 4C cores varies with the Watt budget available and the workloads being run.
With Intel P- and E-cores and with the various ARM core designs things are far more complicated, because there are Watt budgets where an E-core might actually be faster than a P-core for a given workload. And then there are Watt budgts where P-cores simply no longer function, while E-cores still do.
And that is because these cores are actually very different CPU designs, different transistor types, and in the future even with different fab process sizes.
It means with every additional bit of information, there is more opportunities to get it all wrong: accidentally or also intentionally.