News Exclusive: AMD to begin disclosing Ryzen Zen 4c clock speeds and list the missing core counts on official spec pages — much-needed change will brin...

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The only difference between all Zen 4 and a mix of Zen 4 and Zen 4c is the mix of clock boost behaviour. That's something that we don't normally get, unless it's tested by reviewers. All the maximum Zen 4c clock will tell us is that when using more than 2 cores (in a 2+4 configuration), the extra cores will have a certain maximum speed. That's somewhat useful, but a lower boost is expected for any CPUs, regardless of AMD or Intel or number of cores. When going up in the number of cores used, CPUs will drop clock speed anyway.

So while the Zen 4c maximum clock speed is of theoretical interest, it's not of any practical interest unless we know the clock behaviour of other devices, which we are unlikely to get because articles like this one focus on getting the less important specific spec rather than asking for better disclosure of clock behaviour.
 
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I understand their hesitancy.

These chips today are extremely complex beasts as they try to exploit every nook and cranny for an extra bit of performance. And to explain these things to the level of detail that people are satisfied there are no longer hidden snags, would require bringing the audience to the level where they might have been part of the design team.

And not everyone who just loves to complain or start conspirational rumors will want to or be able to get there.

The logic for mixed 4 and 4c cores in TDP limited designs isn't that different from choice for the Ryzen 9 7950X3D to use a mix of CCDs. By the time you've exhausted the heat budget all the non-V-cache cores in the "fast" CCD, the fact that the cores in the V-cache CCD won't be able to reach non-cache peaks is no longer relevant, because with all cores active, everbody will have to take fewer Watts from the power faucet and reduce clocks anyway. It should work out to a very small clock disadvantage overall at 16 fully active cores.

Here with ~15 Watt total power budgets it's somewhat similar: when say in a 2(4)+6(4C) setup the 3rd core get loaded, the faster cores may have to clock down anyway to reduce their part of the total to a point where they are running at very similar clocks to what the 4C cores can sustain as max speeds. The extra dark silicon area that the high-frequency cores need for heat dissipation at their top frequencies doesn't deliver any benefit when the heat doesn't peak the same on the C-cores. Apart from the cache sizes (which probably still differ), there should be no measurable impact on performance, just more dies per wafer.

Of course the optimal relationship between 4 and 4C cores varies with the Watt budget available and the workloads being run.

With Intel P- and E-cores and with the various ARM core designs things are far more complicated, because there are Watt budgets where an E-core might actually be faster than a P-core for a given workload. And then there are Watt budgts where P-cores simply no longer function, while E-cores still do.

And that is because these cores are actually very different CPU designs, different transistor types, and in the future even with different fab process sizes.

It means with every additional bit of information, there is more opportunities to get it all wrong: accidentally or also intentionally.
 
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Just a guess based on what's been spoken of publicly is that AMD didn't really want to disclose the Zen 4c boost clocks because they're going to be a lot lower than Zen 4. AMD has been pushing that nobody would know the difference between Zen 4 and Zen 4c, and that's likely because the all core boost of all Zen 4 vs a mix is probably very close to the same in limited TDP circumstances. AMD doesn't disclose their all core boost speeds though so without that information it would appear as though AMD is lying about the performance.

I look forward to their disclosure just the same as more transparency the better.
 
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As far as AMD disclosed to this day, Zen4c vs Zen4 is only compactified and the L3-Cache has mobile-grade size like mobile Zen3 or Zen4 has, so for each 8-Core CCX 16MB instead of the desktop-grade 32MB L3.
L1, L2 and every other capability is equal, max turbo excluded.
The compatification results in a denser core obviously and because of physics those have lower max turbo.

So in my opinion all AMD need to add is the max turbo of the Zen4c cores.
Same opinion is also for the X3D CCDs max turbo in the 7900X3D/7950X3D.
 
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Ugh very unpleasant read very negative point of view had a bad day??? Unbelievable. quote: But the company hasn't adhered to standard industry practice and divulged clock speeds for the new cores in any fashion. In fact, even the very presence of the smaller and less-performant Zen 4c cores has been absent from the company's main specification pages and marketing materials, leading to claims of deceptive marketing practices. AMD will let us know don t flip, and just my 2 cents I m happy AMD doesn t adhere to standard industry practice, this whole piece could have been alot shorter and a more relevant informative piece without al the assumptions. But yeah have a great day.
 
While a breakdown of Zen 4/4c cores would definitely be good, the clockspeed issue feels more academic than practical? Under a hard single core load you're going to be limited by the boost of the strongest core, while under a sustained load I'd assume you're not running all cores at maximum boost clock anyway.

As for the NPU... is the clockspeed a meaningful spec? I thought software support and TOPS was important, and whether you got there through more clocks or more parallelism wasn't really important at this level.
 
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