News Forget 10nm? Intel May Change CPU Naming Scheme

atomicWAR

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I think Intel should call there 10nm, peanut and butter jelly SANDwhich...that they dropped on the floor. Its still good for consumption, you know five second year rule.
 
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husker

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Recently leaked internal memo from Intel management to their employees: "You're actually making more money than the competition pays their employees. See, once we factor in the dollar value density in units of purchase power per cost of living increase squared' (i.e. Millions of dollars per squared employee). The beauty of this payment strategy is that it takes into account dollar distribution design, which is something that can vary a lot from company to company. You're welcome!"
 

spongiemaster

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Its another game of " We Lost, so we will redefine the game to make us look good again!" nonsense.

Indeed, let us call the 10nm node, Intel's red faced embarrassment node
Intel was the last semiconductor company to accurately label their node sizes. Even today, their measurements are closer to reality than anyone else's. If you'd bother to read the article, you'd see what Intel could be proposing would be much more accurate than the complete nonsense that is used now. But let's dump on Intel anyway, since that's what all the cool kids do.
 
Intel was the last semiconductor company to accurately label their node sizes. Even today, their measurements are closer to reality than anyone else's. If you'd bother to read the article, you'd see what Intel could be proposing would be much more accurate than the complete nonsense that is used now. But let's dump on Intel anyway, since that's what all the cool kids do.
I agree. Though I appreciate the irony that, way back in the day, Intel was trying to sell MHz/GHz measurements, and didn't seem pleased by AMD's PR (Performance Rating, I think was the phrase?) numbers.

Add in the irony that, even today, until Vermeer came out, the Intel crowd would complain about how AMD can't hit Intel's clock speeds, despite the IPC advantage.

I wonder how they're going to reconcile with not using the absolute number anymore?

Ok ok, sarcasm aside, I do like the idea of MTr/mm2 measurement. That said, let's say Intel's 10mm has the same MTr/mm2 as AMD. Does the fact that the Intel version is on a 10nm process vs AMD using a 7nm process mean that there's higher thermal dissipation to deal with per mm2? I would think it does, but that's just a guess. If my guess is correct, though, it should probably be factored in.
 
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Eximo

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Well if they adopt LMC, that would be good. Might force everyone to do it.

Of course Intel could be deceptive here. They know they plan to stack dies together, which could give them a silly way to 'double' their number if they consider the transistor density in a 2D plane. But logically it should only apply to the manufacturing process, not assembly.
 

hotaru251

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Its another game of " We Lost, so we will redefine the game to make us look good again!" nonsense.
not really.

the #nm isnt a standard.

thats why intels 10nm is closer to amd's 7nm

it was a dumb naming scheme to begin with and means nothing now.

actually adopting a standard is best for everyone in long term....now if only they'd also fix their SKU naming...
 
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I've said it before and agree the process node used to make the "chip" is the most overrated performance stat since MHz. IPC and Transistor Density tell you 100x more than clock speed and process node.

That being said, TSMC 5nm node is more dense than Intel's 10 nm node, so no matter what they do with the naming it's not going to change the fact that TSMC currently can produce a denser "chip" with better PPW characteristics.
 

PCWarrior

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When planar transistor scaling stopped, the nomenclature was meant to continue by way of equivalency in transistor density increases. Traditionally the half-pitch of the planar transistor was scaled down to sqrt(2) (that’s ≈0.71x) of what it was in the previous node and that would result in a 2x increase in transistor density in the new node. So when the move was made from planar transistors to 3D FinFETs etc, a new node was meant to be defined by a 2x increase in transistor density. The node would be named after the half-pitch of a hypothetical planar transistor that would achieve that 2x increase in density – that is with a half-pitch shrank to 0.71x. Intel going from 14nm to 10nm represents exactly this philosophy. Intel actually aimed and achieved an even larger increase than just 2x – the original aim was 2.7x – and what was actually achieved, even after the relaxations to improve yields, is still well above 2x. Calling it 9nm would be more accurate than 10nm but anyway.

I don’t know how Intel will end up advertising their nodes but they are not the ones who rendered the nanoscale nomenclature useless. That feat goes to Samsung, Global Foundries and TSMC and their shameless marketing shenanigans. For example TSMC and Global Foundries called their 16nm intranode improvements “12nm”. Using the abovementioned equivalency philosophy a true 12nm process would have represented a 1.78x increase in transistor density. But what the foundries achieved was a mere 5% increase that Intel would not even use a plus sign to represent let alone call it a new name to appear as a new node. All while the 16nm name was not accurate to begin with. On Intel’s scale it would be called 18nm. Anyway, TSMC did move to a new node that was indeed a 2x increase over their ‘16nm’ (which is actually 18nm) node. They called it ‘10nm’. Using Intel’s scale that would land to 0.71x18nm=12.8nm. Since TSMC was calling their previous node ‘16nm’ it could be called “11.4nm”. But then factoring the intranode improvements (called “12nm”) they called it “10nm”. Then there was the move to “7nm”. That according to the equivalency philosophy should have represented another 2x increase in transistor density. But it only achieved 1.6x. Not bad but still not 2x. Even accepting their “10nm” as an accurate name, the new node, given the 1.6x achieved density, should have been named “8nm”. Going by Intel’s scale it would be 0.79x12.78=10nm. The intranode improvements with N7P achieved a further 18% increase in density putting it at 9.2nm on Intel’s scale, ever so slightly behind Intel’s 10nm which is actually around 9nm. Thus there is pretty much complete parity between TSMC's 7nm+ and Intel's 10nm.
 
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Co BIY

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To the untrained eye, Intel's new 10nm SuperFIN architecture sounds a lot less advanced than the TSMC 7nm process AMD uses [
I'm not sure about that, To this untrained eye Intel ( hey that company sounds smart) has "SUPER" in it which is awesome and TSMC (which sounds like it could be a trucking conglomerate?) has "nm" in it which sounds "mmm ... Lame".

In my opinion Intel is already winning the silly marketing game. The fact that by bringing this "controversy" up causes us to talk about the actual near parity shows that they are the marketing geniuses we all hate them for.

Now making fun of AMDs pitiful misleading copycat naming schemes on chipsets and processors is totally worthwhile and would be a much better use of of internet blather.

In conclusion Intel's next process clearly needs to be called "Super-Duper Shark-FIN 4Nano^2"
 
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Hey, maybe they could find a more accurate way to report their processor TDP values while they are at it. : 3
Intel's TDP is super accurate because it's just a simple cut off point that you can set yourself in bios, it's PL1 and PL2 and the only issue is that intel doesn't enforce it so you can put in whatever you want, intel suggests you to put it to 125 but doesn't force you.
AMD on the other hand claims 105W TDP but then forces mobo makers to supply 140W to the socket...it's only 35% more.

TSMC 7-nanometer comes in two variations – low power and high performance. Those cells are 240 nm and 300 nm tall respectively.

The dense cells come at around 91.2 MTr/mm² while the less dense, high-performance cells, are calculated at around 65 MTr/mm².
 

ingtar33

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Well if they adopt LMC, that would be good. Might force everyone to do it.

Of course Intel could be deceptive here. They know they plan to stack dies together, which could give them a silly way to 'double' their number if they consider the transistor density in a 2D plane. But logically it should only apply to the manufacturing process, not assembly.
This post perfectly encapsulates where this is going. Intel will use their 3d stacking to claim x2 density over other chips, ignoring the true number of transistors on the total processor, or other indicators. This is because they know AMD will be on 5nm by the time intel is on 10nm.
 

ginthegit

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When planar transistor scaling stopped, the nomenclature was meant to continue by way of equivalency in transistor density increases. Traditionally the half-pitch of the planar transistor was scaled down to sqrt(2) (that’s ≈0.71x) of what it was in the previous node and that would result in a 2x increase in transistor density in the new node. So when the move was made from planar transistors to 3D FinFETs etc, a new node was meant to be defined by a 2x increase in transistor density. The node would be named after the half-pitch of a hypothetical planar transistor that would achieve that 2x increase in density – that is with a half-pitch shrank to 0.71x. Intel going from 14nm to 10nm represents exactly this philosophy. Intel actually aimed and achieved an even larger increase than just 2x – the original aim was 2.7x – and what was actually achieved, even after the relaxations to improve yields, is still well above 2x. Calling it 9nm would be more accurate than 10nm but anyway.

I don’t know how Intel will end up advertising their nodes but they are not the ones who rendered the nanoscale nomenclature useless. That feat goes to Samsung, Global Foundries and TSMC and their shameless marketing shenanigans. For example TSMC and Global Foundries called their 16nm intranode improvements “12nm”. Using the abovementioned equivalency philosophy a true 12nm process would have represented a 1.78x increase in transistor density. But what the foundries achieved was a mere 5% increase that Intel would not even use a plus sign to represent let alone call it a new name to appear as a new node. All while the 16nm name was not accurate to begin with. On Intel’s scale it would be called 18nm. Anyway, TSMC did move to a new node that was indeed a 2x increase over their ‘16nm’ (which is actually 18nm) node. They called it ‘10nm’. Using Intel’s scale that would land to 0.71x18nm=12.8nm. Since TSMC was calling their previous node ‘16nm’ it could be called “11.4nm”. But then factoring the intranode improvements (called “12nm”) they called it “10nm”. Then there was the move to “7nm”. That according to the equivalency philosophy should have represented another 2x increase in transistor density. But it only achieved 1.6x. Not bad but still not 2x. Even accepting their “10nm” as an accurate name, the new node, given the 1.6x achieved density, should have been named “8nm”. Going by Intel’s scale it would be 0.79x12.78=10nm. The intranode improvements with N7P achieved a further 18% increase in density putting it at 9.2nm on Intel’s scale, ever so slightly behind Intel’s 10nm which is actually around 9nm. Thus there is pretty much complete parity between TSMC's 7nm+ and Intel's 10nm.
Mod Edit - Keep it polite

For those that keep spouting the theoretical crap about the new density measurement are failing to understand the process of PCB design and manufacture, and how multilayer circuits work. Now for the Uninitiated and those that don't understand ASIC design, take a look at Intel's proposed 3D Transistor design that was meant to be the design methodology for their 10nm node. Intel had a great idea but have failed to implement it in any great degree at their 10nm node, and have chosen not to upgrade all its Lithography to the 10nm process, because the Yields from the starts are poor and unpredictable.
Take a look at this
https://hexus.net/tech/news/industry/147520-samsung-3nm-nanosheet-transistor-advantages-described/



https://semiaccurate.com/2011/08/18/intel-moves-transistors-from-2d-to-3d-and-more

Intel Chose to use the Stacked Nanosheet FET design that allows for a 3 transistor per unit area (and it works for 14nm, but not 10nm) of the equivalent Planar tech where as classical design used the Standard FinFET or the dual Fin Fet design that TSMC uses that has a 2 FET per unit area compared to Intel's 3 per unit area. The advantage about the 2 FET design structure is the planar connections are Perpendicular, allowing for the connections to be more simply added without binding to other nano-wires that causes fails in the Lithographic metal layering process. (note that one fail causes a failed core, leading to failure rates). Intel's stacked FinFET design layers 3 on top of each other, not only meaning that the Gate transistor control is difficult to master, but the tech is infinitely more complex that the density that TSMC has. But choosing a simpler Nano tech means lesser density, but far greater success in yields an more easily shrunk size for the transistor. The Transistor size is correct 7nm for TSMC as it is for Intel, the only thing that makes it difficult is the tri-stack and Intel cannot master the 10nm node because even though they have some success with the node, they also have a massive failure rate due to the difficulty of working with the layering and connecting process of all 3 transistors without binding some of the nano wires together.

Enter the Dragon; Samsung has design a process called the GATE ALL AROUND design method, and Samsung has nailed the design using Nanosheets of Germanium-silicon composites for the gate connection allowing it to create the 3D design of Tri-layer design all the way down to 3nm. So TSMC you can mock, but Samsung is Thrashing everyone here with Lithographic size.

Intel took a risk and decided to use Crystalline metals (cobalt) to get around its yield issues (and we will see if that works) but it is still now 3-5 years behind Samsung. who already have a working prototype and are also being transparent in how they are accomplishing what Intel has struggled to perfect since 2011. The solution is not prefect, as germanium has leakage problems in reverse BIAS with transistors, but has a smaller gate control voltage of half of silicone's forward bias voltage. So in Idle, I predict that it will drain more power (unless they have a control circuit that turns off segments of the PCB when not in use, which is mainstream now).

Now on the second point, Intel's density per unit area is compromises of poor thermal design (allowing transistors to be closer that they should be to other transistors) which raises temperature above thermal norms. Chips that go above 70 degrees risk unsoldering themselves over time, and Intel clearly doesn't care about this. it is risking high warrantee failures and compensation, just to stay in the game. Yes it can afford it, but personally, I see a massive desperate move here. Data centers and other large scale computer use based companies would be fools to go with the new Intel chips. it would cost them massively in complex board purchases with aftermarket coolers/throttled processors and massive electricity cost rises per day.

AMD takes the TSMC, approach which is safe, keep the design traditional and keep yields high, and now AMD can keep up with Intel in many IPC benchmarks, while having lower clocks and lower power consumption. It is a win for AMD as they can keep up with half the power, and will sell better to data centres now that look to save money on running costs.

Please stop coming out with uninformed opinions, Intel are desperate , deal with it!
 
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PCWarrior

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For those that keep spouting the theoretical crap about the new density measurement are failing to understand the process of PCB design and manufacture, and how multilayer circuits work.
We are talking about chip/die manufacturing and semiconductor engineering. So PCB design is largely irrelevant.

AMD takes the TSMC, approach which is safe, keep the design traditional and keep yields high.
Well strictly speaking AMD has no manufacturing division so they cannot possibly take TSMC's approach. They simply use TSMC's manufacturing facilities and are using the design tools available. Of course, the big manufacturing decision AMD has made with regards to yields was to use multiple dies/chiplets and not follow the monolithic path that Intel had taken.

and now AMD can keep up with Intel in many IPC benchmarks, while having lower clocks and lower power consumption. It is a win for AMD as they can keep up with half the power, and will sell better to data centres now that look to save money on running costs.
That's the beauty of higher IPC and higher core number. You can use lower frequency and still achieve higher performance all while achieving lower power consumption. That of course applies to applications that are heavily threaded which is what server workloads usually are. It should be noted here that IPC is a per workload metric. Up to and including 3000 series AMD's IPC improvements were what I would call cheap. Make the core wider so you increase throughput per core in a similar manner a larger core count would achieve. That benefited workloads like tile-based rendering that would also scale with more cores but did little to help workloads that wouldn't. 5000 series is a different beast. That being said some of the architectural elements of Zen3 such as unified L3 cache should have been there since Zen 2 at least, not to say since original Zen. It's almost like AMD purposefully introduced a knowingly flawed design with the original Zen only to correct one flaw at a time and appear like making massive IPC improvements each time. That coupled with the fact that they already moved to bigger cache and AMD is slowly running out of some easy core design tricks. They have one more with DDR5 and then I am wondering how good they will be with IPC improvements. I hope they are.
Please stop coming out with uninformed opinions, Intel are desperate , deal with it!
I don’t think anyone doubts the semiconductor engineering advances made by TSMC and Samsung. What is controversial is the naming of the nodes and how nodes of different manufacturers can be compared with one another. And since Intel is compared, in the minds of the uninitiated at least, unfavorably by the current state of affairs and their position appears to be worse than it actually is, they react. And the fact of the matter is that Intel’s 10nm+/10nmSFF is comparable to TSMC’s 7nm/7nm+ so clearly nm naming is no longer a scientific or technical metric but a pure marketing one.

As for the future, Intel’s 7nm slots between TSMC’s 3nm and 5nm nodes. TSMC will be using GAA for their 2nm node, Samsung for their 3nm one and Intel for their 5nm. In any case at least until 2025 Intel will be trailing TSMC. AMD is likely to move to TSMC’s 5nm by the start of next year and stay there until at least late 2023/early 2024. Meanwhile Intel will be using 10nm until mid-2023 so again they will be a node behind for the next 2 years. In mid-2023 Intel will move to their 7nm, at least for mobile surpassing AMD like with Icelake Vs Ryzen 3000 (Zen+) mobile. But then AMD moves to TSMC’s 3nm though this time around Intel will also utilise TSMC and their 3nm for some logic tiles. It will be interesting to see how all these pan out for sure.
 
Intel's TDP is super accurate...
Intel's TDP ratings for their recent generations of processors have been nowhere near representative of their real-world power draw and heat output under typical operating conditions. In many cases these processors are drawing over double the power under heavy loads than what their TDP would imply, or up to several times the power in the case of of their "low-power" chips. The TDP only applies to their base frequency, which one is unlikely to encounter under load on a properly-configured system. The power draw of AMD's Ryzen processors, on the other hand, tends to typically match their advertised TDP almost perfectly.
 
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mrv_co

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As long as Intel continues on the 14nm process, they might as well rebrand their desktop CPUs as Megawatt, Gigawatt, Terawatt, etc.
 
Intel's TDP ratings for their recent generations of processors have been nowhere near representative of their real-world power draw and heat output under typical operating conditions. In many cases these processors are drawing over double the power under heavy loads than what their TDP would imply, or up to several times the power in the case of of their "low-power" chips. The TDP only applies to their base frequency, which one is unlikely to encounter under load on a properly-configured system. The power draw of AMD's Ryzen processors, on the other hand, tends to typically match their advertised TDP almost perfectly.
Their TDP is a digital choke in bios that no software can go over, let alone use twice as much power.
If someone disables TDP from bios or puts it to some ridiculously high value then it stops being intel's TDP.
Also quite the same as with ryzen's turbo issues different software uses different amounts of power and so some will run higher clocks than others, 125 guarantees you the base clock for even the most demanding workload, that's very different from everything only running at base clocks.
 

BogdanH

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Intel's process naming is more accurate, Intel's 10nm is actually very similar to TSMC's 7nm, TSMC's 7nm isn't really 7nm, Intel comes with new "fair" naming idea, etc. Why would we consumer care about that at all?
I don't care why exactly AMD CPU's consume less power than Intel CPU's (except out of curiosity). AMD-TSMC says it's because of their "7nm" process.. so be it. Yes, quite possible Intel and TSMC "nm" processes aren't directly comparable. So what? I'm only interested on finished product: performance, efficiency and price.
My impression about "new naming scheme"... It's Intel's marketing attempt to put consumers in doubts. In sense "AMD's 7nm actually isn't what you think it is". And maybe I would believe that, if Intel would have something to show: a better CPU. Ok, maybe I'm wrong with my impression.. but I couldn't care less.
 
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