FSB Limits Exposed: Intel CPUs Don't Scale Very Well In UC Berkeley Test

[Guest]

Berkeley (CA) - Researchers from the Computer Science Division at UC Berkeley and Lawrence Berkeley National Laboratories (CRD/NERSC) recently submitted a paper to the IEEE, highlighting the subject of scaling an optimized Lattice Boltzmann Simulation on popular supercomputer architectures.

FSB Limits Exposed: Intel CPUs Don't Scale Very Well In UC Berkeley Test : Read more

 

[TripGun]

If the test is so dependent on memory bandwidth then it seems they should have submitted a few GPU's in their test as they are so well known for their throughput. These synthetic benchmarks are optimized for certain core architecture and should be taken with a grain of salt. What are they teaching our kids in school?

 

[Kari]

I wouldn't call LBMHD as a 'synthetic benchmark', they actually use it in their research and stuff.. 😛

 

[StenLi]

"..AMD?s Opteron (Santa Rosa).." r u sure?

 

[traviso]

But did they test the old 65nm Xeons or the new 45nm ones, as they have a much higher FSB (800mhz vs 1033mhz and 1666mhz). I'm suspecting they probably didn't.

Also, Intel has a new chipset coming out in the end of 2008 that totally gets rid of the northbridge/southbridge concept and is promising (no benchmarks yet, but over the past 1.5yrs, Intel has been delivery on promises, unlike the past) to make big improvements in bus limitations for PCs.