News Fujitsu flaunts 144-core Monaka CPU — 2nm and 5nm chiplets, SoIC, and CoWoS packaging

[Admin]

Fujitsu's Monaka is a monstrous processor with four 2nm compute chiplets, 5nm SRAM, and a massive 5nm IO die. This time, without HBM memory.

Fujitsu flaunts 144-core Monaka CPU — 2nm and 5nm chiplets, SoIC, and CoWoS packaging : Read more

 

[bit_user]

So there are only 5 real tiles and the rest are just spacers?

Also, is it not crazy that the I/O tiles is bigger than all 4 core tiles combined?

Anyway, it sounds interesting. Who is designing the ARM cores?

 

[thestryker]

So there are only 5 real tiles and the rest are just spacers?

Everything I've seen indicates that there are only 5 top tiles so if that picture is accurate that's a lot of spacers.

Anyway, it sounds interesting. Who is designing the ARM cores?

Fujitsu designed the prior A64FX so I'd guess this is their own design. They'd talked about doing an enterprise market SoC so I'm guessing this is that.

 

[bit_user]

Everything I've seen indicates that there are only 5 top tiles so if that picture is accurate that's a lot of spacers.

Maybe the eventual goal is to scale up to 216 cores. So, while those tiles are currently blank, they might be more placeholders than spacers.

Fujitsu designed the prior A64FX so I'd guess this is their own design. They'd talked about doing an enterprise market SoC so I'm guessing this is that.

While searching for some insight, I ran across this. It presages the massive cache underpinning the CPU shown here:

Stacking Up L2 Cache, RIKEN Shows 10X Speedup For A64FX By 2028

Let the era of 3D V-Cache in HPC begin. Inspired by the idea of AMD’s “Milan-X” Epyc 7003 processors with their 3D V-Cache stacked L3 cache memory and

www.nextplatform.com

 

[sjkpublic]

No HBM support may be a mistake.

 

[DS426]

No HBM support may be a mistake.

Not so long as there is a severe HBM supply shortage.

 

[bit_user]

No HBM support may be a mistake.

Nvidia didn't use HBM in their Grace CPUs. They claimed that it was like 3x as expensive and lower density than their stacked LPDDR5X solution. Those CPUs each have 72 cores and about 500 GB/s of memory bandwidth. On the package, they can fit 480 GB of memory, whereas the Hopper GPUs maxed out at 96 GB, IIRC.

 

[thestryker]

No HBM support may be a mistake.

Highly doubtful due to the negatives this would cause for the more general purpose enterprise market this seems aimed at.

Some details:
These have a 12 channel DDR5 memory controller which means based on current memory technology a range of ~460GB/s-844GB/s and maximum capacity of 3072GB (assuming 1DPC). Micron has said they're projecting 12800MT/s MCRDIMMs around the same time as these would be hitting the market which means 1228GB/s memory bandwidth.

For context HBM4 is supposed to top out at 16hi 32Gb which is 64GB/stack with ~1638GB/s memory bandwidth. NV's current Blackwell tops out at 8 HBM stacks and I can't imagine more than that being viable cost wise with HBM4. That would end up with a best case scenario of ~10.6x the memory bandwidth and 1/6th the capacity.

So while the extra bandwidth would likely be very good when tailored to specific workloads it eliminates the broader market due to hugely increased cost and limited capacity.

 

[thestryker]

Hopper GPUs maxed out at 96 GB, IIRC.

H100 (SXM/PCIe) is 80GB/96GB with 5/6x 16GB stacks and H200 (SXM) is 141GB with 6x 24GB stacks.