You say that so authoritatively. Are you speaking as a current or former CPU architect?
Certainly not by using MS Excel as the simulation platform.
That wasn't due to lack of simulation, but rather that GCN was optimized for compute workloads. With RDNA/CDNA, they split their GPU architectures, so each could be optimized for its respective workload.
I'm sure the Bulldozer fiasco wasn't simply due to lack of simulation.
Hardware design languages have been around for 30 - 40 years.
CPUs designers have been using simulators for decades. In large measure, they're used for testing & debug, before tape-out, but a chip company I worked at, more than 2 decades ago, was already using C models for performance estimation.
Source? We did RTL-level simulations of our ASICs. You couldn't run a big workload through them, that way, which is why we also used C models.
LOL, you don't need an entire chip-level simulation to tell you that you failed to make your timing targets.