G.SKILL Achieves Fastest Quad Channel Memory Speed

[exfileme]

G.SKILL has broken another record.

G.SKILL Achieves Fastest Quad Channel Memory Speed : Read more

 

[General_McTard]

A 4960x is not a Haswell its a Ivy Bridge-E

 

[General_McTard]

A 4960x is not a Haswell its a Ivy Bridge-E

 

[cloud7s7]

4073 is too high for them, at least for the moment

 

[cloud7s7]

4073 is too high for them, at least for the moment

 

[opmopadop]

How come the link sais "RAM Speed : 2036 MHz (1:18) @ 14-31-15-45"

Or do we double timings for the hell of it when the letters DDR are mentioned?

 

[WithoutWeakness]

How come the link sais "RAM Speed : 2036 MHz (1:18) @ 14-31-15-45"

Or do we double timings for the hell of it when the letters DDR are mentioned?

"DDR" literally means "double data rate". The 2036 MHz in the screenshot is the memory controller's clock speed. Since DDR RAM transfers data twice per clock you calculate the speed of the memory by doubling the clock speed. Thus, the memory clock on the processor is running at 2036 MHz but the RAM itself is running at 4072 MHz.

 

[Pinhedd]

How come the link sais "RAM Speed : 2036 MHz (1:18) @ 14-31-15-45"

Or do we double timings for the hell of it when the letters DDR are mentioned?

"DDR" literally means "double data rate". The 2036 MHz in the screenshot is the memory controller's clock speed. Since DDR RAM transfers data twice per clock you calculate the speed of the memory by doubling the clock speed. Thus, the memory clock on the processor is running at 2036 MHz but the RAM itself is running at 4072 MHz.

Close, but not quite.

The 2,036Mhz is the DRAM IO bus reference clock frequency. For a DDR system, data is transferred on both the rising and falling edge of the reference clock, for a data transfer rate of 4,072 MT/s (Mega Transfers per second).

The DRAM memory modules themselves run much slower than the IO bus. DDR SDRAM has a 1:1 ratio between the SDRAM core clock and the IO bus clock (two IO transfers are performed per core clock). DDR2 SDRAM has a 1:2 ratio between the SDRAM core clock and the IO bus clock (four IO transfers are performed per core clock). DDR3 SDRAM has a 1:4 ratio between the SDRAM core clock and the IO bus clock (eight IO transfers are performed per core clock). The rationale for this is that once an SDRAM row is opened, it is possible to concurrently read or write a large number of columns at once by using a buffer and then serialize them across the IO bus. DDR, DDR2, and DDR3 have doubled the depth of this buffer each generation from one, to two, to four, to eight words.

This relationship between IO transfer rate, IO bus reference clock, and SDRAM core clock gives rise to the rather flat real time latency values seen over the past couple of generations. The IO bus frequency has increased far faster than the memory modules themselves.

For example, DDR2-1066 has an IO transfer rate of 1,066MTs per pin, an IO reference clock of 533Mhz, and a core clock of 266Mhz (1:2 ratio).

DDR3-1066 has an IO transfer rate of 1,066MT/s per pin, an IO reference clock of 533Mhz, and a core clock of 133Mhz (1:4 ratio).

 

[khaledegy200]

Omg! we still didn't get DDR4 yet and look what is out there http://www.dailytech.com/Micron+Samples+Hybrid+Memory+Cube+With+8x+the+Transfer+Rate+of+DDR4/article33446.htm

 

[opmopadop]

The 2,036Mhz is the DRAM IO bus reference clock frequency. For a DDR system, data is transferred on both the rising and falling edge of the reference clock, for a data transfer rate of 4,072 MT/s (Mega Transfers per second).

Thank you. I was just trying to make the point that throwing 'Mhz' numbers around without explanation is confusing. Hence why I indicated that the linked page had one value and that this article doubled that value 'for the hell of it'.

 

[ipwn3r456]

Nobody needs DDR4 RAM anymore with that such high speeds :/

 

[shafe88]

I would like to see this done with an amd apu, with some gaming benchmarks.