News G.Skill pushing new CAMM2 DDR5 memory modules to the overclocking limit — hits DDR5-10000 speeds on modified ASUS motherboard

[Admin]

G.Skill broke DDR5-10000 with a CAMM2 memory module attached to a custom Asus motherboard, showing off its potential for high-performance applications.

G.Skill pushing new CAMM2 DDR5 memory modules to the overclocking limit — hits DDR5-10000 speeds on modified ASUS motherboard : Read more

 

[-Fran-]

I want this. I need this. Pls GIB!

In any case, DDR6 and new sockets would be the best instance to make the switch. Let's see which of the two (or others) has the marbles to make the switch first; or encourage it.

Regards.

 

[Dementoss]

The image provided under the first paragraph, is useless, please publish a larger one, so the figures can be more legible.

 

[chaz_music]

This was a good read. Dell did great thing by helping take their CAMM design and help JEDEC to release the public CAMM2 version for everyone. It goes a long way into reducing the RF transmission path issues that the DIMM and SODIMM sockets caused, which limits the max frequency that can be used. The PCB edge pattern will also help reduce ESD events as long as users handle the CAMM2 boards by the edges like the are supposed to do for all boards. There is a ground guard ring around the CAMM2 design to protect the sensitive tracks. This also helps stop lateral EMI from coming into the edge of the board. Kind of awesome.

And I am super glad that they kept the provision for ECC. I predict that eventually, the industry will make ECC the standard memory configuration just like error corrected SSDs. Nearly all PC bus systems have error correction - except RAM. And yes - DDR5 has ECC at the chip level due to lowering the operating voltage, but not the bus going to the CPU.

The PC industry has made a phenomenal profit off the false ECC "tax" and even made users believe that it is more expensive to make/use. It isn't. You can find ECC on the most mundane $10 MCUs used in embedded applications. A hand full of transistor and some extra I/O pins and you are cooking with gas. We have ECC in our SSDs and just expect it. Why not the RAM?

There is a Google ECC study from 2011 that found a major increase in ECC hits during the solar maxima that year. The paper also concluded that they expected a significant number of Windows BSODs and other system corruptions to be caused by bad RAM reads. And for space-borne applications, I have worked with teams that took this into account and we put more stringent ECC in place. Soft errors are very common, so bit flips should be expected and handled. Most PC busses do that, except non-ECC RAM.

Thank you for the article, Jowi.

 

[dalek1234]

The image provided under the first paragraph, is useless, please publish a larger one, so the figures can be more legible.

If you are on a PC, right-click and select "Open Image In New Tab "(or similar wording), then zoom in on that tab (Ctrl + mouse wheel up/down). The image isn't the clearest, but the text is readable.

 

[John Nemesh]

Need to see this on a consumer AMD platform ASAP!

 

[abufrejoval]

The CRUCIAL number (sorry G.Skill!) I am missing here is the bandwidth actually achieved, because that's where the performance comes from, clocks are perhaps the means, but at this point just a number.

CAMM2 promised to be all about getting near soldered DRAM latencies and bandwidth yet retain DIMM like expandability.

So far I'm just getting all the disadvantages: extra cost, isolated, lock-in implementations, lack of standards or reusability.

Of course, it's a chicken and eggs issue, but it's been years, hasn't it? So far it has a whiff of Rambus.

 

[Eximo]

The number is the bandwidth. 10000 MT/s How memory has been measured for a while. Kind of had to stop using the old PC numbers because they got too ludicrously large. But back then it was MB/s, like PC3200.

 

[Eximo]

So far I'm just getting all the disadvantages: extra cost, isolated, lock-in implementations, lack of standards or reusability.

Of course, it's a chicken and eggs issue, but it's been years, hasn't it? So far it has a whiff of Rambus.

Extra cost until it becomes a normal standard. Though I honestly think it would be short lived regardless. DRAM is likely to end up integrated, and expandable system memory will become another layer, perhaps through CXL.

Not been that long really. CAMM exists from Dell. CAMM2 isn't being sold to consumers, but that is likely a decision against switching tooling mid-cycle. Until the current supply of SO-DIMMs and SO-DIMM boards is used up and it makes sense to transition to new designs.

I think the truth is that most people don't need memory upgrade capability at all. So the soldered solution is fairly easy to do.

I think it would be cool for the desktop, but that is a very small market at this point. OEMs want it cheap, not fast. Enthusiasts are maybe a few percent of the market.

 

[thestryker]

So far I'm just getting all the disadvantages: extra cost, isolated, lock-in implementations, lack of standards or reusability.

Extra cost is obvious and expected for now. I believe the only CAMM2 on the open market currently is the LPCAMM2 from Crucial.

Isolated? Meaning there aren't many implementations? If so that's unfortunately to be expected due to the reality of manufacturing.

Lock-in implementations? what does this even mean? CAMM2 is a JEDEC specification which means any module adheres to that.

Reusability? What's the issue here exactly? They're no different than any other DRAM module specification.

Lack of standards? CAMM2 is a JEDEC standard so no: https://www.jedec.org/news/pressreleases/jedec-publishes-new-camm2-memory-module-standard

 

[dimar]

I was going to buy ThinkPad T16 Gen 4 but decided to wait for the next version with CAMM2 RAM instead.

 

[Mr Majestyk]

One would hope next gen MB's for Zen 6 and Nova Lake would support CAMM2. DDR6 is a long way off for consumers IMO, maybe 2027 but next gen board designs are probably already locked in.

 

[abufrejoval]

Extra cost is obvious and expected for now. I believe the only CAMM2 on the open market currently is the LPCAMM2 from Crucial.

Isolated? Meaning there aren't many implementations? If so that's unfortunately to be expected due to the reality of manufacturing.

Lock-in implementations? what does this even mean? CAMM2 is a JEDEC specification which means any module adheres to that.

Reusability? What's the issue here exactly? They're no different than any other DRAM module specification.

Lack of standards? CAMM2 is a JEDEC standard so no: https://www.jedec.org/news/pressreleases/jedec-publishes-new-camm2-memory-module-standard

There are technical standards and market stanards. Rambus was a technical standard, even saw adoption by Intel, but it failed to be come a market standard and made for expensive RAM that couldn't be recycled in a next generation system.

For me PC has always been about the ability to change and upgrade, reusing what was still good enough for reusing and I don't see CAMM2 getting the kind of traction that it would need to become a market standard.

The bandwidth limitations of dual channel RAM can't really be fixed with higher clocks, if you want more potent iGPUs (for graphics or compute) you need to go wider, perhaps much wider, as the fruity cult does or even Strix Halo, to a degree.

But that becomes expensive, even more so when you go off-chip or die carrier, double or quadruple RAM pins, and you need to accomodate amplifiers for longer traces, adding an extra chiplet in a matching node, die space, power, latencies: LP-CAMM2 may quickly cost as much as DIMMs in power and silicon real-estate, and would CPU vendors want to design just for LP-CAMM2 to optimize power?

How many RAM segments would the market support just within the laptop to desktop market, since most CPU SoC designs are shared among them? Sure, in theory Foveros would allow Lego RAM controllers, but that still needs scale to pay for the flexibility and Intel might no longer get there.

I'm pretty sure the temptation to just stick with soldered RAM and cover perhaps 90% of the market is too big, while a design that allows for everything from soldered to DIMMs doesn't give LP-CAMM2 much of a USP, just extra validation effort.

Current Strix Halo implementations seem to reflect that, each a lost LP-CAMM2 opportunity.

I'd love to be wrong, because I favor flexibility, but somehow PC vendors rarely give me exactly what I want, I guess because more value for me means less profit for them.

 

[thestryker]

How many RAM segments would the market support just within the laptop to desktop market, since most CPU SoC designs are shared among them? Sure, in theory Foveros would allow Lego RAM controllers, but that still needs scale to pay for the flexibility and Intel might no longer get there.

CAMM2 doesn't require anything different from the memory controller because it's literally just an interface for either LPDDR or DDR. The first laptop with CAMM2 used a regular MTL-H SKU just like all these desktop tests have been run on regular RPL/ARL CPUs.

SODIMMs days are numbered because CAMM2 is just flat out better for the laptop use case. I'm not sure when it will happen though since CSODIMMs are on the market and the highest speed AMD/Intel officially support is 6400 which those are.

As much as I'd like to see some movement on the desktop front even if CAMM2 ends up being better I don't really see UDIMMs going anywhere. With a CKD UDIMMs can already regularly get past the highest speed JEDEC has for DDR5 (8800 MT). Perhaps DDR6 will change something, but CAMM2 currently has a big size problem to match the same capacity as UDIMMs. Up to 64GB is pretty compact, but to get 256GB that's 64 memory IC with the most dense on the market.

 

[Dementoss]

If you are on a PC, right-click and select "Open Image In New Tab "(or similar wording), then zoom in on that tab (Ctrl + mouse wheel up/down). The image isn't the clearest, but the text is readable.

Which is what I did but, posting a higher resolution image, would be much better.

I note that, nobody on the staff has bothered to respond.