Gigabyte's Fleet Of 100 Series Motherboards May Hint At DX12 Multi-GPU Capabilties

[Crashman]

Heavy on model numbers, light on specs.

Gigabyte's Fleet Of 100 Series Motherboards May Hint At DX12 Multi-GPU Capabilties : Read more

 

[jimmysmitty]

I find it very surprising to find PCI slots on a board from an upcoming generation. I haven't had any on a board for the past two, especially on a high end board.

I guess it is cool if you need it but very few do these days.

Also I just noticed, the top end board does say "AMD Crossfire" next to the top PCIe lane so I would assume it does support CFX.

 

[PaulBags]

Do we have specs for the 100 series chips yet? Because with this showing I think I'm actually going to be disappointed.

 

[thomasxstewart]

was to be 109 chipset, yet like i7, maybe this is first toper.
drashek

 

[jimmysmitty]

Do we have specs for the 100 series chips yet? Because with this showing I think I'm actually going to be disappointed.

http://wccftech.com/intel-skylake-s-platform-specifications-detailed-z170-100series-chipset-replace-z97-2h-2015/

Pretty much on par with the Z97 chipset. Wasn't expecting much of a change TBH. Maybe more support for M.2, SATAe and NVMe.

 

[InvalidError]

Pretty much on par with the Z97 chipset. Wasn't expecting much of a change TBH. Maybe more support for M.2, SATAe and NVMe.

The DMI bus desperately needs a kick in the pants to adequately support upcoming IO standards. Or they could integrate a few USB3.1 and M.2 interfaces directly in the CPU to take the main bandwidth hogs off of DMI.

 

[jimmysmitty]

Pretty much on par with the Z97 chipset. Wasn't expecting much of a change TBH. Maybe more support for M.2, SATAe and NVMe.

The DMI bus desperately needs a kick in the pants to adequately support upcoming IO standards. Or they could integrate a few USB3.1 and M.2 interfaces directly in the CPU to take the main bandwidth hogs off of DMI.

They are probably working on implementing more controllers into the die shrink.

However, Skylake will have DMI 3.0 which is set to be 8GT/s so it will probably be quite fast compared to 2.0. Guess we will have to wait and see how many links and how fast overall.

 

[jasonelmore]

The Lane layout is like this

20 Lane PCIE 3.0

8x8x4
or 16x GPU with 4 lanes for NVME storage

 

[skipperkins]

I find it very surprising to find PCI slots on a board from an upcoming generation. I haven't had any on a board for the past two, especially on a high end board.

I guess it is cool if you need it but very few do these days.

Also I just noticed, the top end board does say "AMD Crossfire" next to the top PCIe lane so I would assume it does support CFX.

I still use them. You can get cheap PCI cards, and for many tasks they are good enough. I used to use a PCI Intel NIC (board has cheap one), but they I swapped it out for an eSATA card, which I actually no longer use. Most people use them for sound cards. For many cheap motherboards, a $30 Asus sound card is a great investment. I still have an old HT OMEGA Claro sound card that I use. It is PCI.

 

[InvalidError]

However, Skylake will have DMI 3.0 which is set to be 8GT/s so it will probably be quite fast compared to 2.0. Guess we will have to wait and see how many links and how fast overall.

IIRC, DMI3 is supposed to be 5x8G, which would make it twice as fast as DMI2 and just shy from fast enough to host two high-performance NVMe drives without becoming a bottleneck like DMI2 is.

DMI3 already looks like a tight squeeze for modern IOs even before it comes out.

 

[josejones]

WHY didn't Gigabyte mention the new NVMe interface? Seems like that would be as important to mention as the virgin birth of Christ or something (even tho it's only in two of the gospels, LOL)

; )

 

[josejones]

Yeah, seems like a dumb move not to mention NVMe. That appears to be one of only a few upgraded differences. The benchmarks BETTER be outstanding with no more of the standard measly 5% - 7% performance improvement crap that is not even noticeable.

 

[InvalidError]

The benchmarks BETTER be outstanding with no more of the standard measly 5% - 7% performance improvement crap that is not even noticeable.

I bet Skylake will be about 20% faster than Broadwell, 10% of which simply from bumping clocks back up to Haswell Refresh levels, the usual 5-7% IPC improvement on top of that and then whatever is left on DDR4-2133 vs DDR3-1600.

 

[SirKnobsworth]

The Lane layout is like this

20 Lane PCIE 3.0

8x8x4
or 16x GPU with 4 lanes for NVME storage

That's not correct. There are 16 lanes running from the CPU, and up to 20 additional lanes running from the chipset (note however that using all 20 of those lanes would mean no SATA.

 

[InvalidError]

That's not correct. There are 16 lanes running from the CPU, and up to 20 additional lanes running from the chipset (note however that using all 20 of those lanes would mean no SATA.

Skylake will have 20x PCIe 3.0 on the CPU. x16 or x8x8 for GPU(s) and x4 for NVMe or other uses.

On the IO hub, a handful of potential PCIe lanes are shared/programmable between SATA and USB3, which makes sense since it gives board manufacturers a more flexible balance between on-board extras, PCIe slots, NVMe, SATA and USB3 connectors.

 

[Sakkura]

That's not correct. There are 16 lanes running from the CPU, and up to 20 additional lanes running from the chipset (note however that using all 20 of those lanes would mean no SATA.

Skylake will have 20x PCIe 3.0 on the CPU. x16 or x8x8 for GPU(s) and x4 for NVMe or other uses.

On the IO hub, a handful of potential PCIe lanes are shared/programmable between SATA and USB3, which makes sense since it gives board manufacturers a more flexible balance between on-board extras, PCIe slots, NVMe, SATA and USB3 connectors.

That is not correct. Skylake will have 16 PCIe 3.0 lanes directly from the CPU. It will have a DMI 3.0 connection to the chipset, which doubles bandwidth compared to DMI 2.0. The Z170 chipset will have 20 PCIe 3.0 lanes. The H170 chipset will offer 16 PCIe 3.0 lanes, B150 is 8 PCIe 3.0 lanes, and the low-end H110 gets the same crummy configuration as H81 - 6 PCIe 2.0 (!) lanes.

DMI 3.0 is a nice upgrade, but would still bottleneck you if you tried to fully utilize the available PCIe lanes on Z170, or H170 for that matter.

 

[jimmysmitty]

However, Skylake will have DMI 3.0 which is set to be 8GT/s so it will probably be quite fast compared to 2.0. Guess we will have to wait and see how many links and how fast overall.

IIRC, DMI3 is supposed to be 5x8G, which would make it twice as fast as DMI2 and just shy from fast enough to host two high-performance NVMe drives without becoming a bottleneck like DMI2 is.

DMI3 already looks like a tight squeeze for modern IOs even before it comes out.

True but the actual benefit from such high speed SSDs using NVMe on M.2 is pretty small in the consumer market. a 32Gbps connection would be near unnoticeable to most.

It is nice but I would assume that they are working on a way to increase the bandwidth. It actually hasn't been till recent developments that the DMI/QPI interface has even seen proper utilization. Most GPUs don't even full utilize a PCIe 3.0 x16 and are barely bottlenecked by a PCIe 2.0 x16/3.0 x8.

I guess we will have to see what Skylake-E and the next top end socket present in terms of a interface update.

 

[Steveymoo]

Look at that funky pin layout for the CPU socket.

 

[InvalidError]

It is nice but I would assume that they are working on a way to increase the bandwidth. It actually hasn't been till recent developments that the DMI/QPI interface has even seen proper utilization.

The way to increase bandwidth between the CPU and IO hub is simple: integrate the most bandwidth-intensive parts of it. The 100-series chipsets look like an experiment in universal PCIe/USB/SATA gigabit transceivers. Intel also bought out Altera, which means they now also have access to a few generations worth of Altera's programmable MGTs and related soft/hard IP cores.

With ridiculously fast interfaces, pushing nearly everything through the IOH is not going to remain practical for much longer.