GlobalFoundries: Double Patterning Key Problem at 20 nm

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Even Intel needs to change to another method to overcome this. Why wouldn't GF think of that?
 

serendipiti

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[citation][nom]fulle[/nom]Anyone else read this as "GF plans to cut corners on it's 20nm process to try to save money".[/citation]
Not sure, but looks to me like "our 20nm chips will be more expensive than we thought"

[citation][nom]dickcheney[/nom]Thats it, AMD is dead...[/citation]
AMD is not tied to GF, but yes, seems like another door locked to AMD as chip cost will rise at the 20nm node.

Don't know but people look too pessimistic.
Perhaps it's too soon to draw any conclusion... Could be possible that a more expensive process drives to better products.
Perhaps they are saying: we are going the same way intel went, so our products should improve to a better performance level.


 

hannibal

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Hmmm.. could Intel be so kind and sell production capasity to AMD? Now when AMD buys production capasity to anyone that can provide it. GF and TSMC at this moment. How about Intel? Hmmm I think that intel does not sell their production capasity to anyone, but It would be nice to see what would happen :)
 

TeraMedia

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Guys...

What this means is that out of the 10-20 layers of metal on the chip (they were around 9 or 11 a while back; I expect that number has gone up substantially now), the bottom few - which are the ones that are the smallest and closest together (because higher levels cannot be small-featured due to surface bumpiness caused by lower-layer structures) - need to be manufactured as two masks instead of 1. The one problem I see with this is that if you need to have a single metal structure with two close-together features in it, that would require a portion of the structure would be in one mask, and a different portion would be in the other mask, and I don't know if the process can allow for that without causing excessive surface variation at the point of intersection. Is that actually a problem? I can't envision a scenario in which it would be. So ultimately this means that the circuit design tools need to create two masks instead of one, for a given low-level metal layer. The design tools already create multiple layers per mask anyway (positives, negatives, intersections with vias, etc.), so not really a huge issue. Either Intel ran into this too (and notice you didn't hear about it...), or they employ a different technology to lay down and mask their metal layers. I suspect the former.

This does mean that existing masks cannot simply be scaled down, however. So an IC designer such as AMD cannot simply send the same mask binaries and request a smaller process size. Instead, they need to regenerate the mask binaries using the new process rules. Chances are, other differences in the new process would have necessitated this anyway, so again, no big deal.
 

iLLz

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I smell trouble ahead for GF and AMD. I often wondered why AMD gave up its fabs. I mean keeping all this shit in house can only help you going forward. Look at Intel now, they can have R&D guys on the same page as the Fab guys as well as other engineers and it makes for a more cohesive product.
 

pedro_mann

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[citation][nom]hannibal[/nom]Hmmm.. could Intel be so kind and sell production capasity to AMD? Now when AMD buys production capasity to anyone that can provide it. GF and TSMC at this moment. How about Intel? Hmmm I think that intel does not sell their production capasity to anyone, but It would be nice to see what would happen :)[/citation]
I'm sure there is an old 90nm plant somewhere that needs to be decommissioned. I'm sure they might lease that out to a competitor :)
 

seezur

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[citation][nom]hannibal[/nom]Hmmm.. could Intel be so kind and sell production capasity to AMD? Now when AMD buys production capasity to anyone that can provide it. GF and TSMC at this moment. How about Intel? Hmmm I think that intel does not sell their production capasity to anyone, but It would be nice to see what would happen :)[/citation]

It would be nice but it will never happen. In the early days of processor manufacturing Intel could not produce enough chips to meet demand so they had to outsource production of their CPU's. Guess who got the bid...AMD. Once AMD got the ability to produce Intel's chips they started working on their own CPU's based off the x86 architecture. Needles to say this did not make Intel very happy and this is why Intel does not outsource production of CPU's anymore.
 

alidan

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[citation][nom]serendipiti[/nom]Not sure, but looks to me like "our 20nm chips will be more expensive than we thought"AMD is not tied to GF, but yes, seems like another door locked to AMD as chip cost will rise at the 20nm node. Don't know but people look too pessimistic. Perhaps it's too soon to draw any conclusion... Could be possible that a more expensive process drives to better products.Perhaps they are saying: we are going the same way intel went, so our products should improve to a better performance level.[/citation]

chip cost will rise at 20nm... here lets see this here. moving to 20nm would result in 2.5 times more chips in the same area as 32nm, lets put it this way, if the phenom II chips were on a 20nm you would get about 5 times more chips than they got at 45nm and the increased price is more about the tech going into the new process, once the teathing pains are over, the price comes down to production cost + % proffit.
 
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