News Govt Official: TSMC Looking at $32 Billion Investment for 1nm Fab

[Admin]

The cost of new fabs will be enormous, so brace for expensive chips.

Govt Official: TSMC Looking at $32 Billion Investment for 1nm Fab : Read more

 

[peachpuff]

Intel: Behold... 10nm!
Tsmc: 🤣

 

[Co BIY]

Each doubling down on these process nodes is very risky. Someone (TSMC, Samsung or Intel) is likely to run into a limit either physical or financial where smaller isn't better.

Much better to run the risk with government money !

Of course then you have some government official blabbing your plans ahead of schedule.

 

[Bazzy 505]

amusingly enough even N5 TSMC is quite a misnomer, yes the single "fin" part is actually 5nm wide, but the minimum pitch between fins is 28nm, which translates average CGP of 51nm with cell height of 210nm . So there's really no such thing and 5nm transistor.
But that doesn't translate into catchy marketing slongans that well.

TSMC N5 is certainly a great achievement, but actual max logic density is around 137,6 MTr/mm2
Intel 10mn SuperFin process node achieves max logic density 100.8 MTr/mm2 (rouhgly in ballpark of TSMC N7 process)

so yeah it's one generation behind atm, but certainly not as far some would make you believe.

Same story with so called 1nm is basically equivalent of 2 large molecules 😉 till we know what real cell height is and actual min fin pitch, it's all just hot air 😉

 

[bit_user]

Of course then you have some government official blabbing your plans ahead of schedule.

A foundry needs to be fairly public about its plans, because it has to win new business from customers, and they tend to plan out their chip designs well in advance.

Rest assured that all of the details TSMC discloses in its roadmaps are probably protected by several patents, each. And still, they don't reveal enough detail that someone else would easily be able to replicate the innovation.

 

[Marc9751]

amusingly enough even N5 TSMC is quite a misnomer, yes the single "fin" part is actually 5nm wide, but the minimum pitch between fins is 28nm, which translates average CGP of 51nm with cell height of 210nm . So there's really no such thing and 5nm transistor.
But that doesn't translate into catchy marketing slongans that well.

TSMC N5 is certainly a great achievement, but actual max logic density is around 137,6 MTr/mm2
Intel 10mn SuperFin process node achieves max logic density 100.8 MTr/mm2 (rouhgly in ballpark of TSMC N7 process)

so yeah it's one generation behind atm, but certainly not as far some would make you believe.

Same story with so called 1nm is basically equivalent of 2 large molecules 😉 till we know what real cell height is and actual min fin pitch, it's all just hot air 😉

N5 is TSMC's latest node in 2019. However they've got 2 major node updates since then, N4(2021) and N3(2022).

The timeline:
2021 - Intel 7 (100.8 MTr/mm2)
2021 - TSMC N4 (196.6 MTr/mm2)
2022 - TSMC N3 (314.7 MTr/mm2) - entered volume production
2023 - Intel 4 (160 MTr/mm2) - expected


Even if Intel 4 successfully enter volume production in 2023, the density is still behind TSMC N4 node. I would say Intel is 2 nodes behind.

 

[Bazzy 505]

N5 is TSMC's latest node in 2019. However they've got 2 major node updates since then, N4(2021) and N3(2022).

The timeline:
2021 - Intel 7 (100.8 MTr/mm2)
2021 - TSMC N4 (196.6 MTr/mm2) 146MTr/mm2 ( both N4 and N4P) (volume production in latter half 2022)
2022 - TSMC N3 (314.7 MTr/mm2) - 220MTr/mm2 ( expected to enter volume production 2023)
2023 - Intel 4 (160 MTr/mm2) - (expected to enter volume production in 2023)


Even if Intel 4 successfully enter volume production in 2023, the density is still behind TSMC N4 node. I would say Intel is 2 nodes behind.

N4 is still just a refinement of N5 5nm node (even tmsc itself lists it as such in their roadmaps) and you've got a transistor densities completely wrong for both N4 and N3
so still 1 process node behind