In effect it is what it says, it a mechanism to prevent malicious code affecting the kernel / core OS. And allows all other logical processors to go into "rendezvous" why one processor deals with the error correction, when the error is rectified (if it can be) the processors are released. In rendezvous, the processor basically blocks all interupts to it. There is a pretty detailed view on how the OS works in that respect here:All processors that rendezvous have no errors in their registers. - When certain errors are detected in a multiprocessor system, a single processor takes control of the system while other processors enter a rendezvous state. The single processor performs error handling and then releases the other processors from the rendezvous state.
I don't know if that helps, I just wanted to know what it meant
@gardenman can you convert dumps and see if there is anything obvious? I wish axe wasn't so busy
Where did you grab this excerpt from exactly?
You can also see some detail here: https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/itanium-system-abstraction-layer-specification.pdf