Haswell: News, Rumors & Reviews

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tecmo34

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This sticky is to provide a centralized thread to post information (news, rumors & reviews) related to Intel's Haswell.

We don't want close this thread, as we closed the other ones, so remember the forum rules (ToU & RoC) and FOCUS ON THREAD. Personal attacks to another user will be deleted but I hope not to have to do this, we are adult people, so, act like that and don't be an.....

Ivy Bridge discussion has moved!

http://www.tomshardware.com/forum/332628-28-official-thread-discussion

This is a centralised discussion thread for Haswell now.
 

4745454b

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And I was going to seriously ask if we are allowed to post our own personal "theories" on SB/IB or if we have to find it in an article.

Thanks for the links, I'll read them on my lunch break. I haven't heard much about whats coming.
 

tecmo34

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What the point in posting rumours. Already there is enough junk on net that may burn readers pockets or mislead them into taking wrong decisions/purchases.


Better to stick to hard facts or just wait for them to be released.
I agree with you...

I have updated the thread to focus on News, Rumors and Reviews (once released). Facts are important on the matter but many times the initial facts are released as "Rumors", such as leaked road maps.
 

tecmo34

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4745454b: I would focus on articles you come across on the subject matter versus your own personal "theories", unless you have information to backup your "theories" :D
 
That Xbit article is the only one I've seen that claims "normal" overclocking for SNB-E (instead of the effectively multiplier-only overclocking of SNB-M), but I really hope it's true.
Edit: Actually, I found another mention on page 2 of the first article linked below.

This could be the first move by Intel towards splitting the mainstream and enthusiast sectors by actually having a separate product for each. Mainstream users could still overclock safely via multiplier with SNB-M, but the real performance would be had by moving over to the SNB-E which would have multiplier and BCLK/DMI (or whatever they want to call it) overclocking.

Here's a distillation of what I have heard about SNB-E from various sources:
130W TDP
LGA 2011 socket
Four or six cores plus HyperThreading (have seen forumites say 8 core also but haven't seen a slide or article that says so -- maybe I missed it?)
No integrated graphics
Quad-channel memory controller, DDR3-1600 support (1.25v/1.35v memory?)
40 PCIe lanes (32 in CPU plus 8 from PCH; can do dual x16 or quad x8)
PCIe3? (some articles say PCIe2 others say PCIe3)
Up to 15MB L3 cache
Extreme Edition(s) mentioned
Multiplier overclocking (maybe only Extreme Editions?)
DMI overclocking? (now two mentions)

Another article: A Look Into Intel's Next Gen Enthusiast Platform : Sandy Bridge E & Waimea Bay
Yet another article: Ivy Bridge chipset model names revealed alongside more Sandy Bridge-E details
 

fazers_on_stun

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Semiaccurate says Intel's 22nm will be using FinFETs:

http://semiaccurate.com/2011/04/07/intel-goes-finfet-on-22nm-somewhat/

Also, the onboard GPU might get beefed up to 16 or 24 execution units, and maybe stacked lowpower DDR2 on the chip itself:

http://semiaccurate.com/2010/12/29/intel-puts-gpu-memory-ivy-bridge/
 

ghnader hsmithot

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I kinda of like the way intel does its business.Its like the improvements are in increments.Even though some might find it strange.But it spreads out its product and gives us more choices.
And if Sandy bridge come cheaper cuz of ivy bridge every1 would have one by next year.
 

tecmo34

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Here is some information I've come across (Unofficial - Official :D )

■Sandy Bridge-E is scheduled to be released in Q4 (looks to be early Q4'11).
■Ivy Bridge, which is the 22nm die shrink, will be released in Q1'12.
■Z68 chipset should be able to use Ivy Bridge with only a bio update.
 

fazers_on_stun

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Good to know - I'm waiting on Newegg to get some Asus or Gigabyte Z68 boards in, or else I'll drive the half-hour to Microcenter where I can get the 2600K for $279 :).
 

fir_ser

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Today Intel is organizing a press conference at 9:30am PDT, where it will be making its “most significant technology announcement of the year.”
As far as what I’m aware of, Intel should discuss its upcoming 22nm process technology.
So I wonder what will Intel announced with regards to Sandy Bridge-E and Ivy Bridge.

The link to this event is: http://www.intc.com/eventdetail.cfm?EventID=96649
 

fazers_on_stun

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^ Well this is what I was expecting - FinFET or Tri-Gate transistors as Intel is calling them now. There have been rumors about Intel using FinFETs ever since the 45nm node.

So I imagine that 22nm Atom SoC's will be very competitive in the cellphone & tablet markets, esp. if Intel combines it with the stacked DDR2 memory for the HD4000 GPU, or whatever it'll be called (16 or 24 EU).

I also now think that perhaps Ivy Bridge will be more than 20% faster in the same power envelope than Sandy Bridge - as the article states, the 22nm transistor is almost 40% more performance than the 32nm transistors Intel uses in Sandy Bridge..
 

ghnader hsmithot

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I am a bit doubtful of this technology.I hope it gives us more performance.Just doubtful of the problems.
 

fazers_on_stun

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Well the problem with ever-shrinking process nodes is that the leakage currents tend to rise rapidly as a percentage of all currents. For example, at 45nm the leakage between the gate and the channel in a FET is significant, despite the fact that the insulator (SiO2) is basically pure glass. When that layer of glass is mere nanometers in thickness, even a ~1V potential difference between the gate and the channel will cause a significant amount of charge leakage. That current multiplied by the potential difference is just wasted energy that shows up as heat. Which is why Intel introduced HKMG that reduces the leakage signficantly, and which Global Foundries is now using at 32nm.

Another even bigger problem is the channel leakage - the residual current between source and drain - when the transistor is supposed to be OFF. Transistors are not really ideal ON/OFF switches - they alternate between mostly ON and mostly OFF, which means they waste power in either state, plus the parasitic capacitances cause them to waste energy when switching from one state to the other. Eventually as the process shrinks, more energy is wasted than actually used in performing useful computations, and that wasted energy shows up as unwanted heat. AMD uses Silicon-On-Insulator (SOI) wafers which greatly reduces the parasitic capacitance, at least at the larger nodes like 90nm, probably does not have as significant a benefit at the smaller nodes, because the above leakage currents start to outweigh the parasitic effects.

Tri-gate FinFETS reduce the channel leakage by a huge amount, relatively speaking, since now the charge carrier (electrons in N-channel FETs, holes in P-channel) now have to get past 3 potential barriers vs. one when the transistor is nominally "OFF". If each barrier gives an exponential tail-off, then the total leakage current will be significantly reduced.

Or at least that's how I imagine it works, given that I had solid-state physics and design some 20+ years ago :p...
 
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