ghnader hsmithot :
I am a bit doubtful of this technology.I hope it gives us more performance.Just doubtful of the problems.
Well the problem with ever-shrinking process nodes is that the leakage currents tend to rise rapidly as a percentage of all currents. For example, at 45nm the leakage between the gate and the channel in a FET is significant, despite the fact that the insulator (SiO2) is basically pure glass. When that layer of glass is mere nanometers in thickness, even a ~1V potential difference between the gate and the channel will cause a significant amount of charge leakage. That current multiplied by the potential difference is just wasted energy that shows up as heat. Which is why Intel introduced HKMG that reduces the leakage signficantly, and which Global Foundries is now using at 32nm.
Another even bigger problem is the channel leakage - the residual current between source and drain - when the transistor is supposed to be OFF. Transistors are not really ideal ON/OFF switches - they alternate between mostly ON and mostly OFF, which means they waste power in either state, plus the parasitic capacitances cause them to waste energy when switching from one state to the other. Eventually as the process shrinks, more energy is wasted than actually used in performing useful computations, and that wasted energy shows up as unwanted heat. AMD uses Silicon-On-Insulator (SOI) wafers which greatly reduces the parasitic capacitance, at least at the larger nodes like 90nm, probably does not have as significant a benefit at the smaller nodes, because the above leakage currents start to outweigh the parasitic effects.
Tri-gate FinFETS reduce the channel leakage by a huge amount, relatively speaking, since now the charge carrier (electrons in N-channel FETs, holes in P-channel) now have to get past 3 potential barriers vs. one when the transistor is nominally "OFF". If each barrier gives an exponential tail-off, then the total leakage current will be significantly reduced.
Or at least that's how I imagine it works, given that I had solid-state physics and design some 20+ years ago
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