Question HBM Memory Organization - Load/Store Operations ?

[rajsng3737]

Are the basics of HBM the same as that of DRAM? i.e., when an LLC miss request goes to DRAM, the whole 64B block corresponding to that address is fetched from DRAM. But that block is transferred in 4 transactions(16B at a time, because channel width is 16B). In HBM memory, a requested block of 64B will also take 4 transactions or it will be transferred in 1 transaction only?

 

[Ralston18]

What do you think or believe to be the answer?

I am asking primarily because the question appears to be an exam or a homework question.

Per Forum rules we cannot take tests or do homework for posters.

No way to truly know from this end....

No harm here in providing or stating how you would answer the question. And support that answer as necessary by citing some resource(s) or links.

Post accordingly.

 

[rajsng3737]

What do you think or believe to be the answer?

I am asking primarily because the question appears to be an exam or a homework question.

Per Forum rules we cannot take tests or do homework for posters.

No way to truly know from this end....

No harm here in providing or stating how you would answer the question. And support that answer as necessary by citing some resource(s) or links.

Post accordingly.

I was reading some research papers and got this doubt, there is not much information about the actual working of dram that's why I asked.

 

[Ralston18]

What specific doubts do you have regarding HBM and DRAM?

FYI:

https://www.techtarget.com/searchst...will store bits of,at the column is activated.

And for more details look for links similar to the following link:

https://www.allaboutcircuits.com/te...duction-to-dram-dynamic-random-access-memory/

Also - regarding research papers: Source, Author(s)?

If you have questions and /or are questioning something then consider contacting the author(s).

Especially if you are also in the academic community.

 

[rajsng3737]

What specific doubts do you have regarding HBM and DRAM?

FYI:

https://www.techtarget.com/searchstorage/definition/DRAM#:~:text=DRAM will store bits of,at the column is activated.

And for more details look for links similar to the following link:

https://www.allaboutcircuits.com/te...duction-to-dram-dynamic-random-access-memory/

Also - regarding research papers: Source, Author(s)?

If you have questions and /or are questioning something then consider contacting the author(s).

Especially if you are also in the academic community.

I got the answer, so what actually happens is, each channel in an HBM memory is having two half banks. Now these half banks is having a channel width of 64bit. Inside half banks there are multiple banks(0-7). On an access all the banks(inside an half bank) will provide one one byte of data constituting 64bit(8 bytes) and with a burst length of 4 we will be able to get 32Bytes on a single access to a half bank. So in total to transfer 64B we only need to access a half bank twice.
Source - https://ieeexplore.ieee.org/document/9643473


Where as in dram the channel width is either 8, 16 or 32 bit. So if considering the general case of 16 bit channel width and a burst length of 8 then on a single access, we can only transfer 16 Byte ( 8x16bit (2byte) ) so we will actually require 4 accesses in case of dram even with the burst length of 8 which is double that of hbm bank burst length which was 4.


And we cannot increase the dram channel width by a lot because we are constrained by the physical pin counts in the dimm slot. But the same constraint is not there in hbm thus, a very large overall channel width of 1024 bits (64 bit per channel).

 

[Ralston18]

And how will what you have learned be applied?

Is it knowledge for just the sake of knowing (which is a good thing) or do you have a real world problem that can now be addressed based on the answer that you have learned?

Just curious - rhetorical question.

 

[rajsng3737]

Actually I was trying to simulate hbm memory in a micro-architecture simulator. So needed to write the correct code for it. And for the correct code I needed to know the correct working of hbm. How the access pattern was different from dram.