Help! Dual-core Opteron: 1-way, 2-way ????

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Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

I am a little confused with this terminology and could not find
much information in AMD site.

I would like to confirm (or be corrected on) the following:

1) It is my impression that these dual-core Opterons are *truly*
two processors in one physical casing. That is, plus/minus
any external interface circuitry, or bus controller, etc. to
coordinate/synchronize the two CPUs. Also, perhaps they do
share the L2 cache? (as I understand, each of the two CPUs
has its own 64k+64k L1 cache -- correct?)

2) If, for instance, I am going to install Linux on a dual-core
Opteron beast, then I would use the SMP kernel (IOW, a dual-
core chip provides indeed an SMP architecture)

My confusion comes when I read about the 1-way, 2-way, etc.
models. It has always been my impression that N-way refers to
the number of processors in an SMP architecture. Shouldn't
the minimum N for a dual-core be 2? I mean, it sounds as
though the N in N-way refers to the number of chips we put
(i.e., the number of CPU sockets on the motherboard). Is
that the case? (doesn't make a lot of sense to me, but if
that's what it is, I would like to know it)

Please clarify these concepts. The uncertainty is killing me

Regards,
-Mike

 

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Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Mike Gonzalez wrote:
> I am a little confused with this terminology and could not find
> much information in AMD site.
>
> I would like to confirm (or be corrected on) the following:
>
> 1) It is my impression that these dual-core Opterons are *truly*
> two processors in one physical casing. That is, plus/minus
> any external interface circuitry, or bus controller, etc. to
> coordinate/synchronize the two CPUs.

Two cores, each with its one caches, in one chip. Each chip hasa
cross bar for communicating between the two cores, one memory
controller shared by the two cores, and a System Request
Interface shared by the two cores.

> Also, perhaps they do
> share the L2 cache? (as I understand, each of the two CPUs
> has its own 64k+64k L1 cache -- correct?)

They have separate L1 and L2 caches.
>
> 2) If, for instance, I am going to install Linux on a dual-core
> Opteron beast, then I would use the SMP kernel (IOW, a dual-
> core chip provides indeed an SMP architecture)
>
> My confusion comes when I read about the 1-way, 2-way, etc.
> models. It has always been my impression that N-way refers to
> the number of processors in an SMP architecture. Shouldn't
> the minimum N for a dual-core be 2?

Unless your software is priced per core instead of per CPU, why
do you really care ?

However, so far the standard for x86 is that n-way refers to the
number of CPUs, not the number of cores.

I suspect we are going to have to come up with a new convention
for talking about things like this. My vote is for something
like 4 x 2 to indicate 4 dual-core chips and 2 x 4 to indicate 2
four core chips.

> I mean, it sounds as
> though the N in N-way refers to the number of chips we put
> (i.e., the number of CPU sockets on the motherboard).

N-way continues to refer to the number of *occupied* CPU sockets
on the motherboard.

> Is
> that the case? (doesn't make a lot of sense to me, but if
> that's what it is, I would like to know it)
>
> Please clarify these concepts. The uncertainty is killing me
>
> Regards,
> -Mike

 

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Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

On Wed, 08 Jun 2005 14:38:52 -0400, Mike Gonzalez
<mgonz19761205@yahoo.ca> wrote:

>I am a little confused with this terminology and could not find
>much information in AMD site.
>
>I would like to confirm (or be corrected on) the following:
>
>1) It is my impression that these dual-core Opterons are *truly*
> two processors in one physical casing.

Yes.

> That is, plus/minus
> any external interface circuitry, or bus controller, etc. to
> coordinate/synchronize the two CPUs.


All the synchronizing stuff was built into the Opteron/Athlon64 core
right from the get-go. They're just now making use of this circuitry
by tossing another processor onto the same die. The external
interface remains exactly the same as for a single-core processor.

> Also, perhaps they do
> share the L2 cache? (as I understand, each of the two CPUs
> has its own 64k+64k L1 cache -- correct?)

Both L1 and L2 caches are separate in current Opteron designs.

>2) If, for instance, I am going to install Linux on a dual-core
> Opteron beast, then I would use the SMP kernel (IOW, a dual-
> core chip provides indeed an SMP architecture)

Most definitely yes.

>My confusion comes when I read about the 1-way, 2-way, etc.
>models. It has always been my impression that N-way refers to
>the number of processors in an SMP architecture. Shouldn't
>the minimum N for a dual-core be 2? I mean, it sounds as
>though the N in N-way refers to the number of chips we put
>(i.e., the number of CPU sockets on the motherboard). Is
>that the case? (doesn't make a lot of sense to me, but if
>that's what it is, I would like to know it)
>
>Please clarify these concepts. The uncertainty is killing me

You aren't alone here, this has been a fairly large issue for the past
couple years in the lead up to multi-core chips. Do you refer to the
number of processor according to the number of cores or the number of
sockets? AMD, Intel and Sun have decided to talk about things on a
per-socket basis. IBM and HP talk about things on more of a per-core
basis. If you buy a dual-core Opteron, AMD counts that as a single
chip. If you buy a dual-core Power5, IBM counts that as two
processors.

This is not only important from our own understanding of just how many
cores we're buying, but also from a software licensing point of view.
With Linux you might not have to worry about this much, but a lot of
major software is sold on a per-CPU basis. If you want to buy a copy
of Oracle, you don't just pay a flat fee, you pay a certain amount
according to the number of CPUs in the system you're running. So in
this case it can mean a LARGE difference in cost if the number of CPUs
are measure per-socket or per-core.

-------------
Tony Hill
hilla <underscore> 20 <at> yahoo <dot> ca

 

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Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Rob Stow wrote:
> Mike Gonzalez wrote:
>
>>I am a little confused with this terminology and could not find
>>much information in AMD site.
>>
>>I would like to confirm (or be corrected on) the following:
>>
>>1) It is my impression that these dual-core Opterons are *truly*
>> two processors in one physical casing. That is, plus/minus
>> any external interface circuitry, or bus controller, etc. to
>> coordinate/synchronize the two CPUs.
>
>
> Two cores, each with its one caches, in one chip. Each chip hasa

Oops. Typos. /s/one caches/own caches/, /s/hasa/has a/

> cross bar for communicating between the two cores, one memory
> controller shared by the two cores, and a System Request
> Interface shared by the two cores.
>
>
>>Also, perhaps they do
>> share the L2 cache? (as I understand, each of the two CPUs
>> has its own 64k+64k L1 cache -- correct?)
>
>
> They have separate L1 and L2 caches.
>
>>2) If, for instance, I am going to install Linux on a dual-core
>> Opteron beast, then I would use the SMP kernel (IOW, a dual-
>> core chip provides indeed an SMP architecture)
>>
>>My confusion comes when I read about the 1-way, 2-way, etc.
>>models. It has always been my impression that N-way refers to
>>the number of processors in an SMP architecture. Shouldn't
>>the minimum N for a dual-core be 2?
>
>
> Unless your software is priced per core instead of per CPU, why
> do you really care ?
>
> However, so far the standard for x86 is that n-way refers to the
> number of CPUs, not the number of cores.
>
> I suspect we are going to have to come up with a new convention
> for talking about things like this. My vote is for something
> like 4 x 2 to indicate 4 dual-core chips and 2 x 4 to indicate 2
> four core chips.
>
>
>>I mean, it sounds as
>>though the N in N-way refers to the number of chips we put
>>(i.e., the number of CPU sockets on the motherboard).
>
>
> N-way continues to refer to the number of *occupied* CPU sockets
> on the motherboard.
>
>
>>Is
>>that the case? (doesn't make a lot of sense to me, but if
>>that's what it is, I would like to know it)
>>
>>Please clarify these concepts. The uncertainty is killing me
>>
>>Regards,
>>-Mike