News Here’s the CPU Intel Accidentally Revealed, Then Pulled From Public View

[Admin]

Intel has modified its promotional video on advanced packaging technology to remove a processor that the company didn’t want to show.

Here’s the CPU Intel Accidentally Revealed, Then Pulled From Public View : Read more

 

[derekullo]

Silly Intel!
With those pictures alone I will start up my own Fab and start mass producing my own chips!
This will be their greatest blunder!

... besides 14nm++++

 

[JayNor]

"For all we know, Intel can use the same I/O chiplet for Granite Rapids and Sierra Forest."

Intel has stated that Granite Rapids and Sierra Forest shared the same platform, although they also have said that Sierra Forest would not support above 2S configurations ... which implies there could be some restriction on the number of HSIO lanes used for UPI.

 

[dalek1234]

578 mm²? That's a bit on the FAT side. What am I missing here? I thought the purpose of chiplets was to produce smaller dies to keep the cost down due to better yields?

 

[jp7189]

578 mm²? That's a bit on the FAT side. What am I missing here? I thought the purpose of chiplets was to produce smaller dies to keep the cost down due to better yields?

..or to pack a single package with more silicon than the reticle size limit would normally allow.

 

[PEnns]

I guess using "leaks" each time is getting too obvious....

 

[kjfatl]

578 mm²? That's a bit on the FAT side. What am I missing here? I thought the purpose of chiplets was to produce smaller dies to keep the cost down due to better yields?

It is apparent that this die has many identical cores. Each time a chiplet is halved in size the usable area drops by about 20%. The alternative it to include redundant cores that are unused if they fail test. Even if 20% of the cores have failed, Intel will have a saleable part.