Here's something you don't see everyday: 90nm silicon piss..



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A firm, Chipworks, claims that UMC's 90nm process isn't really a 90nm
process (just a reduced 130nm process), and it also claims that it's not
using low-k dielectric, but is using fluoro-silicate glass (FSG).

UMC counters that, it's 90nm process *does* meet the standard for 90nm as
set out by the International Technology Roadmap for Semiconductors (ITRS).
Also it's 90nm process can be optionally offered in either low-k or FSG
(though its website never mentions this option).

Additionally, UMC claims that it's found a new technique for boosting the
efficiency of SOI transistors.

Seems like the last one is a face-saving announcement after being battered
by allegations earlier in the week.

Actually, it seems that there are a lot of direct attacks between companies
these days. Is Chipworks trying to make a name for itself? Is it working for
another firm to discredit UMC? What's the point of it all, I wonder?

Yousuf Khan

Humans: contact me at ykhan at rogers dot com
Spambots: just reply to this email address ;-)


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Yousuf> What's the point of it all, I wonder?

The second EETimes article you reference has this sentence:
> Independent analysis of engineering details has become more common at
> the 90-nm process node as it has become harder to reach the metrics
> set by the ITRS.

This statement is unattributed and unsupported in the article, which
suggests to me that it came from someone who wants to encourage its
truth. Maybe someone at Chipworks.

In any case, there are missing details here. Chipworks looked at one
chip and found no low-k dielectric at the bottom. Does anyone know if
Xilinx *asked* UMC to use low-k at the bottom? Xilinx may not have
wanted that process option. Processes are not sold on a
it basis to large volume, early adopter customers like Xilinx. The
customer has a lot of input on how much risk they want to take, and in
what way. And risk management is very much a part of the 90nm
apparently everyone had a lot of suprises in the 130nm generation.

The gate length shows another missing detail here. I can just imagine
someone looking at a chip and trying to reverse engineer the process
details. Suppose they happened to cut through the PLL. Most of the
transistors in our PLLs are not drawn to the limits specified by the
fab, in many different ways: some gate lengths are longer than
most of our poly endcap and heads are much longer than minimum, and
metal pitches are quite big compared to what is possible. You could
draw some very bad conclusions from looking at the wrong part of the
chip, or even from looking at the wrong chip! What if Xilinx was
concerned about leakage through super-short gates?

Finally, I wonder about this roadmap everyone is supposed to be on.
roadmap is a loose agreement, primarily so that process equipment
can plan what to develop when. But CPU and ASIC processes have been
diverging for a while -- it might be like DRAM and logic were ten
ago. The gate shrink schedules for the two are definitely different
the schedules for the CPUs may have just taken a Right Hand Turn*).
schedule is the "Roadmap" endorsing?

* I've heard that "Right Hand Turn" is Intel's codename for the P4
cancellation decision. That's cute, and may give some insight into
the corporate angst they've been going through.