Hot Chips 2017: Intel Deep Dives Into EMIB

[Guest]

Intel presented the company's new EMIB (Embedded Multi-Die Interconnect Bridge), a technique that provides high-speed communication between several chips, at the yearly Hot Chips semiconductor conference.

Hot Chips 2017: Intel Deep Dives Into EMIB : Read more

 

[JamesSneed]

So would Intel's marketing department say they are gluing chips together for EMIB?

 

[redgarl]

AMD is gluing chips together, however Intel is providing innovation... cmon, they are in pure damage control and they understand they were wrong since Rysen came into play.

 

[kinggremlin]

What AMD is doing with their CPU's is not what Intel is developing here. Glue jokes aside, the underlying concept of connecting multiple identical fully functional cpu's to act like a single die higher core cpu like AMD is doing is not new. Intel did that way back with their initial dual core Pentium D and I'm sure they weren't the first.

What Intel is developing with EMIB is more akin to a modular processor. The separate glued together parts (Intel is calling them chiplets) are not the same and do not have to be fully functional processors on their own. Whether or not you want to call it innovative really isn't relevant, because it is a very interesting concept that could lead to the development of products not possible today.

 

[JamesSneed]

What AMD is doing with their CPU's is not what Intel is developing here. Glue jokes aside, the underlying concept of connecting multiple identical fully functional cpu's to act like a single die higher core cpu like AMD is doing is not new. Intel did that way back with their initial dual core Pentium D and I'm sure they weren't the first.

What Intel is developing with EMIB is more akin to a modular processor. The separate glued together parts (Intel is calling them chiplets) are not the same and do not have to be fully functional processors on their own. Whether or not you want to call it innovative really isn't relevant, because it is a very interesting concept that could lead to the development of products not possible today.

Honestly its an evolved version on the same concept. AMD will be glueing a Vega core to their Zen cores for their SoC. I get it Intel is making this like it's the best thing ever, showing how they can have different parts with different lithography etc but the AMD way also would allow the Vega to be on 7nm and the Zen core could be on 14nm. Intel is just taking it a step further and allow smaller functional pieces to be "glued" which is pretty interesting but It is a bit ironic that they are taking "gluing" to the next level right after making that a negative point for AMD's Zen based products.

It's rather obvious both sides think monolithic cores are a thing of the past when they start going to smaller process nodes.

 

[alextheblue]

It's rather obvious both sides think monolithic cores are a thing of the past when they start going to smaller process nodes.

Well, except for Intel's marketing department.

 

[Wisecracker]

Harmonizing the Industry around Heterogeneous Computing

Let's take a look at the scoreboard:

Advanced Micro Devices & Partners . . . . . . ►77
Chipzilla . . . . . . . . . . . . . . . . . . . . . . . . . ►01

( Is there a 75-Run Rule in the IT Industry ? )

 

[msroadkill612]

Fine, but Intel are just playing air guitar as a spoiler.

We have already seen the sudden appearance of similar "me too" white papers from nvidia re gpu mcmS.

What is the object here? Its to boost HB interlink performance where pcie3 struggles - ie. linking storage/memory/gpu/cpu/nvme.

Clearly, linking the gpu is the greatest mainstream challenge for pcie. Intel do not make a decent GPU, so they are back to square 1 - they have to get nvidia to play ball with a chiplet for intels mcm.

With the imminent release of raven ridge apu, amd will have IN PRODUCTION, examples of these resources interlinked separately& independently from the pcie bus, using the Fabric bus.

Maybe not all in one place, but working examples of having the problem areas covered well & economically, either now or soon.


There is not a lot of other call for chiplets. PCIE handles the low bandwidth details stuff pretty well as is. The real (HB) problems, will have been sorted for millions of happy amd customers long before intels mcm is a reality, in the usual 5 years a fresh product takes.

For example, the pro vega ssg gpu card has 2TB of raid 0 nvme ~storage/cache extender & 16GB of gpu ram. They are all linked on on the discrete vega fabric bus.

Similarly, on amdS imminent apu, we see vega gpu and zen cpu interlinked using infinity fabric.

The age old problem of teaming multi processors, reduces largely to one of maintaining coherency between them.

There is little doubt fabric works excellently at teaming cpuS, judging from Ryzen, & fabric has surely always been planned as including both amds cpu & their gpuS.

AMD have all the ingredients and skills, & are not many steps away from the killer hedt+ product - an APU MCM with multi core cpu, multi gpu, hbm2 cache with nvme ~storage/cache.

If it requires the space of 2x MCMs for high end products, a 2 socket mobo could accommodate that.

 

[Aspiring techie]

Now if Intel combines a CPU and 8GB of HBM2 into one package, they could see massive gains in performance using the HBM2 as a last level cache.

 

[dealcorn]

Now if Intel combines a CPU and several carefully selected chiplets into one package, they could see massive gains in performance in bunches of application areas.

 

[Wisecracker]

... What is the object here? ...

The objective is to productively link disparate processing platforms and peripherals into a power proficient unified 'virtual' computing system.

In other words, everything including the kitchen, sync'd (sorry for the craptastic pun) together under a system arch and OS. Heterogeneous literally means "made up of different parts" that are not uniform.

AMD (and partners) have been slogging away on heterogeneous 'Fusion and 3D-IC' for 10 years now -- including the past 5+ years under the banner of the HSA Foundation. Intel's objective appears to be muddying the heterogeneous waters with proprietary IP -- not the open standards promoted by the HSA partners.

The primary keys to 'bolting together' everything from ARM SoCs, x86 CPUs, programmable chips and SIMD "GPU" compute engines tend to build upon interconnection, coherency, unified memory addressing and OS operability.