Sudarshan Govindaraghavan :
Pinhedd :
Leakage current has no effect on the state of the CPU. CPUs use static CMOS logic for most combinational circuits, so combinational logic loading capacitor is always connected to a supply rail which acts as a strong driver, rendering any impact from leakage moot. The same is not true for dynamic logic, which relies on the ability of a capacitor to hold a certain charge level over a period of time while floating, but that's not really relevant.
The impact of leakage current is most felt in power dissipation. In particular, it's characterized as static power consumption which creates a power consumption floor independent of circuit switching, which is dynamic power consumption.
I guess CPUs use dynamic logic...they use clock signals to control logic circuit outputs unlike static cmos circuits.
Leakage current is a problem for modern cpus...as gate length is reduced,tunneling leakage increases and limits performance..
Are you sure that CPUs use static cmos...?
source:http://en.wikipedia.org/wiki/Leakage_(electronics)
CPUs do use static combinational logic (in particular, CMOS logic). CMOS combinational circuits are unclocked, but they are usually initiated and terminated by a clock synchronized registers formed by edge triggered D-flip-flops. A classical positive-edge-triggered DFF can be constructed from six two-input NAND gates. It's still a static component though.
Static elements can hold their state indefinitely and do not need to be refreshed. CPUs do have a certain minimum clock frequency, but this is the result of how the clock signals are generated and how multiple clock domains are synchronized.
DRAM on the other hand does have to be refreshed periodically, either manually by the memory controller or by triggering an auto-self-refresh routine inside of the DRAM IC. If a row is not sensed and recharged within a certain amount of time, enough charge will leak out of the cell capacitor to render the state of the row unreliable.
Leakage current is most definitely a problem for CPUs, as it contributes greatly to the device's power consumption, failure rate, and lifespan. It does not result in data loss though.
A good way to model leakage current in a capacitor is to place a resistor in parallel with the non-leaky model of the capacitor.
A good way to model leakage current in a transistor is to place resistors between the gate and the source/drain, as well as a resistor between the source and the drain. This is not wholly analogous to the quantum tunnelling effect, but it will result in a similar power consumption model.
In an ideal world, the resistance of all of those resistors would be infinite, but as the processing nodes have shrunk the components have become increasingly leaky which was causing static power consumption to skyrocket. Many manufactures addressed this problem temporarily by increasing the dielectric strength of the gate oxide layer, which pushes up the amount of energy that a hot carrier requires to tunnel through it. Intel also created a rather nice variation on FinFET (which they call 3D-TriGate Transistors) that allows for a long and narrow transistor channel that still has good switching and conduction properties. It's incredibly hard to manufacture, but the performance speaks for itself.