How big is a single RAM cell?

[stichtom]

Hello everyone, I am studying on my own how the PC works and I can't understand one thing. A 32 or 64 bit processor differs for its ability to allocate 2 ^ 32 or 2 ^ 64 addresses for the cells of the RAM. What I do not understand is how big a single cell is. Is a single cell big 32 0r 64 bit or it is not linked with the architecture of the CPU? Thanks so much and sorry for the poor english.

 

[hairystuff]

A single cell of memory is capable of holding either a on state (high (1bit)) or off state (low(0bit)) of data making the cell 1 bit in size, the address bit size is dependent on the memory type and controller and also on memory bank configuration/layout.

 

[Pinhedd]

Hello everyone, I am studying on my own how the PC works and I can't understand one thing. A 32 or 64 bit processor differs for its ability to allocate 2 ^ 32 or 2 ^ 64 addresses for the cells of the RAM. What I do not understand is how big a single cell is. Is a single cell big 32 0r 64 bit or it is not linked with the architecture of the CPU? Thanks so much and sorry for the poor english.

Hi,

Intel's 32 bit microprocessors have been capable of addressing more than 2^32 unique addresses since 1995. It's a technology called Physical Address Extension, or PAE. 32-bit microprocessors that support PAE can be configured to use a larger physical address space of at least 36 address bits, often more. This hasn't changed much, even Intel's high end Sandybridge-E/Ivybridge-E microprocessors (and their Xeon E5 equivalents) have a physical address space of only 40 bits while the ultra high end Xeon E7 microprocessors have a physical address space of 44 bits. 32-bit microprocessors (or 64-bit microprocessors operating in compatibility mode) have a virtual address space of 32-bits, while 64-bit microprocessors operating in long mode (aka 64-bit mode) have a virtual address space of 48 bits.

Processes address memory virtually, and the hardware either maps the virtual address to a corresponding physical address or generates a page fault if no mapping is found.

From the perspective of general purpose computation, each address represents and indexes an 8-bit byte. A 32-bit address space using 8-bit bytes can address 2^32 bytes, or 2^2 * 2^30, or 4 gigabytes. This is not a technical requirement though, as many application specific devices may use non-byte address spaces.

For example, a specific device may use a 32-bit address space to address a 16-bit value instead. It's entirely up to the device designer, the byte is simply convenient and standard for general purpose computation.

That's a bit of a diversion from your question, but since you're studying PC internals I figured that I'd throw that in there. Feel free to ask me some more questions if you find that a little bit confusing.

Anyway, moving on to a bit about the physical size of memory.

The size of a RAM cell depends largely on the type of memory used to construct that cell, and the lithographic process used. The three most common types of primary memory are registers (usually D-Flip-Flops), static RAM, and dynamic RAM.

Registers are really cool. A register is basically a clock synchronous single single-bit storage device. When the register receives both a clock signal and an enable signal it will sample the data at its input and present that data at its output. The output will persist until the register is reset or new data is written (via a clock + enable). There are an enormous number of registers on a CPU, but only some of these can be addressed directly via CPU instructions.

A lot of work has gone into designing efficient registers. Typically a register consists of about nine MOSFET transistors per bit.

SRAM behaves similarly to a register with the exception that it is used in combination with a control interface that hides the internal memory from the external device. A very large number of SRAM cells are placed in an addressable structure and the address is used to determine which SRAM cells are read from or written to. Since much of the control logic is moved to the interface, each SRAM cell is constructed from six MOSFET transistors per bit.

DRAM is a whole different beast. While registers and SRAM use static logic (meaning that the logic output is connected directly to a power supply at all times), DRAM stores the value of a bit by charging or discharging a capacitor. Like SRAM, DRAM uses a control interface, it is not possible for an external device to control a DRAM cell directly. Each DRAM cell is constructed from a single capacitor and a single transistor. This allows DRAM to be much denser than SRAM, but comes at the cost of using dynamic logic.

DRAM must be periodically refreshed. In a perfect world this would not be necessary, but in reality charge tends to leak into or out of the capacitors that store the memory. Over time the memory cell will lose its value and approach an indeterminate state.

DRAM is also much slower. The value that is stored on the capacitor must be determined and converted into a format that is usable. This is accomplished using a positive feedback amplifier and takes quite a bit of time to complete. Modern DRAM chips store memory in what are called "rows" with each row either 8,192 bits wide or 16,384 bits wide. When a row is opened, each cell in the row is sensed into a row buffer which converts it into static logic. The contents of the row buffer can be read by the memory controller and overwritten by the memory controller if need be. When the memory controller is done with the open row, the contents must be written back to the dynamic logic backend. This is called "precharging".

Over time the size of the actual DRAM cells (a modern 4 gigabit DDR3-SDRAM chip has 4 * 2^30 of these, and a single-sided 4 gigabyte DIMM will have eight of these chips) has been dwarfed by the control electronics that are necessary to provide the external interface. The reason for this is that while the transistors and capacitors that make up the dynamic logic have shrunk substantially over time, the analogue components such as the amplifiers have not.