How identify ECC non-registered memory?

FUBARinSFO

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Mar 27, 2009
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Given an ECC memory module (e.g. double-sided 2x9 stick with ECC chips), how do you identify whether or not the module is registered vs. non-registered? Memtest86 v3.4 doesn't provide that distinction (that I can tell).

-- Roy Zider
 
Solution


Hi,

I'm going to use this image as a reference, it is a DDR2-RDIMM...


Hi,

All registered modules will have an additional chip located in the middle of the board (on both sides if the module is dual-rank). DDR2 RDIMMs will have two additional chips, one smaller than the other with both being easily distinguished from the DRAM ICs themselves; DDR3 RDIMMs combine the functionality of the two chips into one. This additional chip is a register and PLL and serves to buffer the address, command, and clock signals.

ECC modules as you mentioned have an additional DRAM IC to store the 8 check bits
 
I'm afraid "an additional chip" is a bit unclear.

All the chips here are DDR-1. I've got a 1GB ECC non-registered DIMM (as labeled) with 2x 9 chips (dual sided), and no 'extra' chips in the middle whatsoever.

I've also got a variety of DIMMs labeled as registered, 2x 9 dual sided, with the chips in the middle splitting the memory 5-4. But there are generally three chips sometimes the same, other times 2 same, one different. One SimpleTech 1GB ECC module has only two, dissimilar, middle chips.

I'm unclear what to make of this. Thank you for your help.

-- Roy Zider


 


Hi,

I'm going to use this image as a reference, it is a DDR2-RDIMM

high_res_vlp_rdimm.jpg


Note that there are 9 identical DRAM ICs in a 4-5 split. 8 of these are for data and the 9th is for the check bits. This is what forms the ECC aspect of the module, without ECC it would be a 4-4 split.

In between the 4-5 split are three additional chips. One large, one moderate, and one really tiny.

The large one is the command and address buffer. It takes the command and address signals from the bus, latches them, and replays them to the integrated circuits. The result of this is that the memory controller only has to drive one register IC per rank rather than nine DRAM ICs per rank.

The moderate sized one is the clock PLL. It serves the same purpose as the register but operates differently.

The tiny one (located between them) is an I2C EEPROM, called the Serial Presence Detect, or SPD. These are present on all memory modules, independent of ECC and registers. The system firmware reads the SPD to determine the manufacturer's specifications for the memory module such as the capacity, supply voltage, timings, etc...

On DDR3 modules the large and moderate sized chips have been integrated into a single chip. It is still much larger than the EEPROM and is easily distinguished from the DRAM ICs.

Some registered DDR2 modules may have been manufactured with a single chip rather than two, but I'm not sure about this.

I believe that the same DDR2 layout (seperate register and PLL chips) is also used in DDR RDIMMs.

If those chips are absent, then the module is not registered.

If you are still unsure, feel free to post pictures and I will determine it for you.
 
Solution
Great description -- and picture. Thank you -- this is the sort of reply that you seldom see. ASUS tech support, for instance, failed even the basic information as to the extra chips on the module. Pathetic.