How much data

[Ned_Flanders]

is held 'inside' at CPU at anyone time when processing at full load? Excluding the L1 and L2 caches. To be more specific, lets for the sake of argument, say I'm talking about a Venice core AMD Athlon 64 skt 939.

 

[Ned_Flanders]

...anyone.

I'm talking about the maximum amount of data being transmitted through the transistors at anyone time.

 

[pat]

Really hard to tell.. Some instructions can use 3 clocks while some can be performed with only one.. Add that to the register holding value ..

So, If you want to know, download the AMD CPU spec, try to find the number of clock cycle for each, add them, then dive by the number of instruction.. That will give you the average clock cycles for each instruction.

Then, take the number of stage the pipeline has, divided by the average clock cycle for instruction and that will give you the average number of instruction processed when the pipeline is full. Do the same with the fpu, ... Don't forget the branch predictor that hold data triying to predict which one willcome next.. And the registry that hold adresses and data.. they mostly change at each instruction and depending of which instruction is performed..

MOVE AX,ffff
BRN AX
...

Damn.. My assembler is so far.......

 

[Ned_Flanders]

Man Pat, I didn't know how techy you are. Well done mate.

And...wow, I'm not doing that...shall we just say 356bytes?

 

[pat]

well.. if most istructions are ported from the 8 bits time, then...well..

Let say 6 instructions might be in the pipeline at one time.. well put 2 x8bits instruction, 2x16 bits instruction and 2x 32 bits instruction. that is roughly 112 bits. Let say the fpu as the same number..112 bits.

Not, I don't remember how many registers, but let say 8, and they are all full with 32 bits .. we are now at 480.. let say that there is 160 bits still running in the cpu in various units.. that is 640 bits... divided by 8, which is 80 bytes ....