Time to steal some more ip... amiright?!?
First, I never heard of 3.5nm node. Secondly, There were more thorough discussions (attached below) about the IP issue regarding how Chinese engineers applied the self-aligned multiple patterning (SAMP), both single-material and dual-material schemes, to continue scaling in Semiwiki already. Actually, Chinese researchers have made pioneer progress in this area in the past 15 years and have been granted some important SAMP processing (US) patents. Intel reportedly applied the dual-material SAQP process to make at least their N10 M1 layer, but they didn't pay anything to Peking University that owns the related patent.
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( First single-material SAQP paper was published by AMAT in 2011 SPIE Adavanced Lithography, but they didn't apply for a patent. So it has been globally used in FEOL fin step for free. The dual-material SAQP patent to use etching selectivity to solve the EPE issue, however, to my knowledge was invented in 2015 and patented by Peking University in 2017 (US patent: 9679771 B1). I guess Intel used it to at least fabricate N10 M1 (see TechInsights report), but Intel did not pay for it, for which PKU was discussing a law solution! There are two SAQP patents that are hot recently. The SiCarrier SAQP variant (CN CN117080054 A) is quite normal and will not be discussed here; the other one is from HiSilicon (CN 117751427 A), which extended 2x SALELE to 4x SALELELE..., the problem is that it requires too many masks (7-8), and the yield may be close to 0! The critical issue is not density multiplication such as 4x, it is the very small cuts/blocks and vias (12-16nm) that need to be self-aligned, otherwise they will miscut/mis-connect the wrong metal lines. The real shock is HiSilicon has a 7x (SASP which can drive down metal pitch to 12nm) patent that incorporate self-aligned vias & cuts (WIPO patent application # CN2022/097621). Details of this patent was just disclosed in the paper titled "Mandrel/spacer engineering based patterning and metallization incorporating metal layer division and rigorously self-aligned vias & cuts (SAVC)” in 2024
SPIE Advanced Lithography+
Patterning.)