News Huawei patent reveals 3nm-class process technology plans — China continues to move forward despite US sanctions

[Admin]

Huawei's self-aligned quadruple patterning patent covers both 3nm and 5nm process technologies, which would allow SMIC and China to create more advanced chips despite the ongoing U.S. sanctions.

Huawei patent reveals 3nm-class process technology plans — China continues to move forward despite US sanctions : Read more

 

[usertests]

Do the 7/5 nodes compare well to TSMC/Samsung/Intel on transistor density, efficiency, etc.? Could be innovation in naming.

 

[Deleted member 2731765]

That's a very OLD patent application link though. No 3nm info as well.

 

[ThomasKinsley]

Make it first. Make it cheaper second. The thing is China doesn't even need to be profitable in the high tech sector for a long time. Profits from mass-produced lower-tier chips will cover the costs, and any remainder that is left will be more than helped by state subsidies. The only thing that sanctions can reasonably do is force China to overcome technical hurdles on their own, but that isn't hard since China poached industry leaders long ago.

 

[EyadSoftwareEngineer]

I'm laughing so much now on US sanctions on China, now China reached nod even smaller than TSMC!.
It has been said many times that if you want to lose an industry to China, just try to restrict it in China.

 

[peachpuff]

I'm laughing so much now on US sanctions on China, now China reached nod even smaller than TSMC!.

Does it count if its only on paper?

 

[ThomasKinsley]

Does it count if its only on paper?

A good question for Intel. 😉

 

[_Shatta_AD_]

Does it count if its only on paper?

Regardless whether this is only on paper or even real. Statistically speaking, if there’s one country in this world that could overcome hurdles and not take restrictions sitting down would be China. I don’t even need to list examples, cause there’s just too many. Look no further than their space program. It’s just a matter of time. US sanctions can only delay the inevitable if not actually sped it up.

 

[TJ Hooker]

The patent linked doesn't seem to mention anything about 3nm (or any other specific nodes) and, as pointed out above, is several years old. So where exactly is this article's claim about this technique is going to be used for 3nm coming from?

 

[TJ Hooker]

now China reached nod even smaller than TSMC!.

TSMC achieved volume manufacturing of their N3 node over a year ago. There is no evidence that any Chinese fabs are currently capable of 3nm. How exactly have they "reached nod (sic) even smaller than TSMC"?

 

[Deleted member 2731765]

Yes exactly. There is no mention of 3nm in the linked patent as well, as it is an old application !

 

[dazzleworth]

I was right the limits of DUV could be pushed to achieve 3nm. Of course ASML needs to sell its so called latest EUV tech, hence planned obsolence. Its the same in the consumer world.

Having DUV 3nm would buy China time to develop its own EUV tech once their mature their homegrown EUV tech

 

[hotaru251]

US sanctions can only delay the inevitable

thats all they do to begin with.
It stops 1st party sales of stuff but they can easily get it through black market and/or develop it themself in time.

ignoring politics its beneficial long term as it gives rise to more competition in market.

 

[anonymousdude]

I was right the limits of DUV could be pushed to achieve 3nm. Of course ASML needs to sell its so called latest EUV tech, hence planned obsolence. Its the same in the consumer world.

Having DUV 3nm would buy China time to develop its own EUV tech once their mature their homegrown EUV tech

First, the patent or linked article doesn't mention 3nm on DUV using SAQP so I don't know where they are getting that from.

Second, just because something is possible doesn't mean it's viable at scale. SMIC is forced to try this because it has no other choice. All the other fabs have moved on from DUV for leading edge because it's not economically viable for them. You can call it planned obsolence if you want. Others will just call it progress or superior tools.

 

[Murissokah]

I'm laughing so much now on US sanctions on China, now China reached nod even smaller than TSMC!.
It has been said many times that if you want to lose an industry to China, just try to restrict it in China.

It hasn't, at least not yet. Probably for some time. Still, this was a very foreseeable consequence. Cutting China off from microelectronics supply chain could never work as a sustained deterrent, it will only slow them down for a while.

 

[Jimmy_CYJ]

There was a detailed discussion about the development history of SAQP (4x) process. It was invented by neither Intel nor SiCarrier/Huawei, and we should not get it confused with two patents recently filed (and widely reported) by SiCarrier and Huawei . The patent reported in this article (and covered by Bloomberg as well before) was filed by SiCarrier but doesn't seem to be production worthy to me (e.g., for BEOL). A more aggressive & practical patterning patent: SASP(7x) filed by Huawei was just disclosed in this year's SPIE Advanced Lihtography + Patterning. This SASP(7x) process incorporates selfa-aligned vias & cuts, can potentially drive metal pitch down to ~12nm (about 1nm logic node) with acceptable yield. The comment attached below is from SemiWiki (slightly revised) and very helpful for us to understand more details about this critical semiconductor technology competition between two nations:

First single-material SAQP paper was published by AMAT in 2011 SPIE Adavanced Lithography, but they didn't apply for a patent. So it has been globally used in FEOL fin patterning for free. The refined dual-material SAQP process to use etching selectivity to solve the EPE issue, however, to my knowledge was invented in 2015 and patented by Peking University in 2017 (US patent: 9679771 B1). I guess Intel used it to at least fabricate N10 M1 (see TechInsights report), but Intel did not pay for it, for which PKU was discussing a law solution! There are two (also called) “SAQP” patents that are very hot in the media recently. But it's easy to have both of them confused with the SAQP process already clearly defined by our chip industry. First one is the SiCarrier SAQP variant (CN117080054 A) which is quite normal (not production worthy) and will not be discussed here; the other one is from HiSilicon (CN 117751427 A), which extended 2x SALELE to 4x SALELELE..., its problem is that it requires too many masks (7-8), and the yield may be close to 0! The critical issue is not density multiplication such as 2x or 4x, it is the very small cuts/blocks and vias (12-16nm) that need to be self-aligned, otherwise they will miscut/mis-connect the wrong metal lines. The real production worthy process is another patent also filed by HiSilicon: a SASP(7x) SAVC technology which can drive down metal pitch to 12nm (about 1nm logic node). This process incorporates self-aligned vias & cuts, and metal-layer division to decouple the power rails from signal wires (WIPO patent application # CN2022/097621). Details of this patent was just disclosed in the paper titled "Mandrel/spacer engineering based patterning and metallization incorporating metal layer division and rigorously self-aligned vias & cuts (SAVC)” in 2024SPIE Advanced Lithography+Patterning.

 

[WhteTrash]

It was only 2 years ago when we saw articles about how China will be stuck with their 30 nm chips because of US sanctions and now they are already at 3 nm.

Hilarious how the "sanctions" are backfiring at the US.

 

[Silas Sanchez]

I really respect China, they are doing all they can to oppose the Imperialist greedy capitalists who really only care about their own superiority. The west spent so many decades selling out their own land which is why nothing is made in England,Australia,US anymore. That is what capitalism does, the US debt is good grounds that their greedy way of life isn't sustainable anymore and their only hope is to rely on made in China, its really quite funny. They are just antagonistic because they cant stand their own power is being challenged by someone else, they are biased and are getting what they deserve. History shows, all great powers come to an end.

I will continue to do my best to support China by buying made in China, certainly wont buy made in US, China quality is getting very very good in all areas now its actually pretty scary.

You cant stop China, they are gonna rise up and oppose and counter US actions. I cant wait until we can buy Chinese branded gpus, so we are no longer forced to pay the capitalist extortion tax to a US company that gets their stuff made in China. Hopefully it will happen and soon.

 

[TJ Hooker]

There was a detailed discussion about the development history of SAQP (4x) process. It was invented by neither Intel nor SiCarrier/Huawei, and we should not get it confused with two patents recently filed (and widely reported) by SiCarrier and Huawei . The patent reported in this article (and covered by Bloomberg as well before) was filed by SiCarrier but doesn't seem to be production worthy to me (e.g., for BEOL). A more aggressive & practical patterning patent: SASP(7x) filed by Huawei was just disclosed in this year's SPIE Advanced Lihtography + Patterning. This SASP(7x) process incorporates selfa-aligned vias & cuts, can potentially drive metal pitch down to ~12nm (about 1nm logic node) with acceptable yield. The comment attached below is from SemiWiki (slightly revised) and very helpful for us to understand more details about this critical semiconductor technology competition between two nations:

First single-material SAQP paper was published by AMAT in 2011 SPIE Adavanced Lithography, but they didn't apply for a patent. So it has been globally used in FEOL fin patterning for free. The refined dual-material SAQP process to use etching selectivity to solve the EPE issue, however, to my knowledge was invented in 2015 and patented by Peking University in 2017 (US patent: 9679771 B1). I guess Intel used it to at least fabricate N10 M1 (see TechInsights report), but Intel did not pay for it, for which PKU was discussing a law solution! There are two (also called) “SAQP” patents that are very hot in the media recently. But it's easy to have both of them confused with the SAQP process already clearly defined by our chip industry. First one is the SiCarrier SAQP variant (CN117080054 A) which is quite normal (not production worthy) and will not be discussed here; the other one is from HiSilicon (CN 117751427 A), which extended 2x SALELE to 4x SALELELE..., its problem is that it requires too many masks (7-8), and the yield may be close to 0! The critical issue is not density multiplication such as 2x or 4x, it is the very small cuts/blocks and vias (12-16nm) that need to be self-aligned, otherwise they will miscut/mis-connect the wrong metal lines. The real production worthy process is another patent also filed by HiSilicon: a SASP(7x) SAVC technology which can drive down metal pitch to 12nm (about 1nm logic node). This process incorporates self-aligned vias & cuts, and metal-layer division to decouple the power rails from signal wires (WIPO patent application # CN2022/097621). Details of this patent was just disclosed in the paper titled "Mandrel/spacer engineering based patterning and metallization incorporating metal layer division and rigorously self-aligned vias & cuts (SAVC)” in 2024SPIE Advanced Lithography+Patterning.

The source for the above comment, if anyone's curious, comment #6 here: https://semiwiki.com/forum/index.ph...-method-for-making-more-advanced-chips.19883/

Edit: However, as far as I can tell, the patent doesn't say anything about the patterning technique enabling sub-5nm nodes or ~12nm metal pitches with DUV, as claimed by the commenter. And I can't access the associated SPIE article other than the abstract (which also doesn't mention either of the claims above). I'm still not seeing any evidence supporting the claim in this Toms article.

 

[Jimmy_CYJ]

The source for the above comment, if anyone's curious, comment #6 here: https://semiwiki.com/forum/index.ph...-method-for-making-more-advanced-chips.19883/

Edit: However, as far as I can tell, the patent doesn't say anything about the patterning technique enabling sub-5nm nodes or ~12nm metal pitches with DUV, as claimed by the commenter. And I can't access the associated SPIE article other than the abstract (which also doesn't mention either of the claims above). I'm still not seeing any evidence supporting the claim in this Toms article.

It's indeed difficult for people who are not within this field to quickly get it. When we talk about 5nm or 3nm nodes of logic chips, the key technical index is the minimum metal pitch of standard logic or SRAM cells. For example, the minimum metal pitch of TSMC 5nm node is 28nm (fin pitch is 28-30nm). The DUV resolution limit (pitch) is about 76-80nm. If we take 80nm pitch as the minimum DUV lithographically defined pitch, a further reduction of pitch by non-optical technique such as SAQP (4x) will result in 80/4=20nm which is smaller than TSMC 5nm-node minimum metal pitch. And obviously, it can also reach the 3nm-node minimum metal pitch as well (typically 22-24nm). But SAQP(4x) cannot get down below 20nm pitch which is required at 2nm node. In short, beyond 3nm, we need more aggressive shrinking process and that's why SASP(7x) was proposed, it can get down to (80/7~12nm) metal pitch roughly corresponding to 1nm logic node.

 

[Sangheili112]

That's a very OLD patent application link though. No 3nm info as well.

The best ones china put out videos saying they can create 5nm by hand