ARICH5 :
whoa, another one. vitual lanes?
The easiest way to explain it is like this: A CPU core consists of two parts. The first part are the CPU registers that holds the cores Architectural State. The second part consists of the Execution Resources that perform actions on the data stored in the CPUs registers.
In a SMT capable CPU, the Architectural State (registers) are duplicated, but the Execution Resources are not. As a result, the Operating System sees double the amount of CPU cores, and can schedule twice as many threads as a result. Because the cores hardware is only partially duplicated, we call these cores "Virtual Cores" to differentiate them from standard CPU cores.
Because the Execution Resources are not duplicated, the OS thread scheduler needs to be aware the processor is SMT capable so as not to schedule threads that need access to the same Execution Resources at the same time, which would result in one thread stopping while the other finishes, providing no benefit (and in some cases, negative benefit). But when handled properly, you can double throughput while only duplicating as little as 10% of a cores hardware.