IBM 90 nm in trouble also

[juin]

http://www.eetimes.com/semi/news/showArticle.jhtml;jsessionid=EHHZDWX2DW4S2QSNDBGCKHY?articleID=19502091

Look that intel is not the only one.At sillicon strategie the guy was saying that for reaching stability it need higher VCC.Presccott end up with much more VCC that intel was planning.So i wonder if we have hit the limit of normal litographie.EUV may come faster that expected.

i need to change useur name.<P ID="edit"><FONT SIZE=-1><EM>Edited by juin on 05/05/04 01:34 PM.</EM></FONT></P>

 

[sonoran]

Meyerson said the biggiest reason is the need for thin gate oxides on the order of a half-dozen atoms.

He's talking about gate oxides 6 <b>atoms</b> thick. And everyone here wonders why upping the Vcore is a bad idea on 90nm chips.

 

[Schmide]

<A HREF="http://www.eetimes.com/semi/news/showArticle.jhtml;jsessionid=EHHZDWX2DW4S2QSNDBGCKHY?articleID=19502091" target="_new">http://www.eetimes.com/semi/news/showArticle.jhtml;jsessionid=EHHZDWX2DW4S2QSNDBGCKHY?articleID=19502091</A>

Dichromatic for your viewing plesure...

 

[juin]

Power consumation scale linear with clock speed but when raising the VCC is scale per power.

EE have just a part of the interview silicon stategy a longer version but you need to fill the registration form.

i need to change useur name.

 

[juin]

He's talking about gate oxides 6 atoms thick.


Which is pretty bad also Low-k around 90 nm will start leaking load of current.High-K will be need in few year.

i need to change useur name.