News Imec Reveals Sub-1nm Transistor Roadmap, 3D-Stacked CMOS 2.0 Plans

[Admin]

Imec, the most advanced semiconductor research firm in the world, recently shared its silicon and transistor roadmap at its ITF World summit in Antwerp, Belgium.

Imec Reveals Sub-1nm Transistor Roadmap, 3D-Stacked CMOS 2.0 Plans : Read more

 

[InvalidError]

If PCB physics hold up at the nano-scale, signal layers will still require power/ground planes to carry high-speed return currents and mitigate crosstalk even if the bulk of power is distributed on the backside.

 

[bit_user]

I'm just wondering if/when we'll reach a point that chips will wear out after months of intensive use, rather than years or decades. Either that, or we could see ECC and other redundancies starting to eat into some of the gains made by further density & efficiency improvements.

This chart really needs an update through 2022, to include Zen 3, Zen 4, Sunny Cove, and Golden Cove. Not to mention Neoverse N1 and V1. Plus, they ought to clarify whether they're talking about server CPUs (which I assume).

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Also, I'd like to see projections of how many transistors per $, since the increasing cost of new nodes could ultimately be the limiting factor on chip complexity.

 

[elforeign]

Thank you for this update, it's very interesting to see where the industry is headed in terms of design and the innovation therein.

I've been following the industry closely since the CELL Processor, which is what initially inspired me to learn more about semiconductor production and design.

I remember some of the early 2K industry roadmaps estimating 1nm designs around 2020 and here we are still marching towards that milestone.

 

[elforeign]

I'm just wondering if/when we'll reach a point that chips will wear out after months of intensive use, rather than years or decades. Either that, or we could see ECC and other redundancies starting to eat into some of the gains made by further density & efficiency improvements.

Also, I'd like to see projections of how many transistors per $, since the increasing cost of new nodes could ultimately be the limiting factor on chip complexity.

I ran various Intel/AMD chips 24/7 running 100% utilization and overclocked for years on end on BOINC. No chips ever failed or caused issues. I'm convinced it's pretty hard to "wear a chip out" unless the user really doesn't know what they're doing or for those niche cases of overclockers really pushing the physical boundaries of the chip design with exotic cooling.

 

[InvalidError]

Also, I'd like to see projections of how many transistors per $, since the increasing cost of new nodes could ultimately be the limiting factor on chip complexity.

With stacked transistor layers, I think we may see a revival of Moore's law as applied to transistors per dollar, though this may come at the expense of lower voltages and clocks to keep thermal density in check.

 

[bit_user]

I ran various Intel/AMD chips 24/7 running 100% utilization and overclocked for years on end on BOINC. No chips ever failed or caused issues.

That's backwards-looking. If you look at the roadmaps in this article, they're talking about shrinking down to atomic structures. I think you can't assume CPUs and GPUs will always be so resilient. These chips could become much more of a "consumable resource" than how we're used to thinking of them.

Just look at what's happened with NAND and now even DRAM! The higher the density gets, the more dependent they're becoming on error-correcting technologies to make them work reliably.

 

[InvalidError]

That's backwards-looking. If you look at the roadmaps in this article, they're talking about shrinking down to atomic structures. I think you can't assume CPUs and GPUs will always be so resilient.

I wouldn't worry too much about the wear aspect of it: as stuff gets smaller, voltages have to go lower to keep both conductive and electron tunnelling leakage in check. The extreme purity requirements of all materials and process accuracy could be a challenge for manufacturing yields when you get to the point where you basically cannot afford to have any atoms out of place or even be the wrong isotope of a given element

If you meant resilience in terms of how easily bits can be flipped by radiation, that could certainly get problematic as activation energies get smaller. This could definitely dictate the practical limit of how small transistors can get in stuff where random errors aren't tolerable.

 

[bit_user]

I wouldn't worry too much about the wear aspect of it: as stuff gets smaller, voltages have to go lower to keep both conductive and electron tunnelling leakage in check.

The article said they haven't been able to go below 0.7 V.

If you meant resilience in terms of how easily bits can be flipped by radiation, that could certainly get problematic as activation energies get smaller. This could definitely dictate the practical limit of how small transistors can get in stuff where random errors aren't tolerable.

An old boss of mine once did a research project for a government lab, to design radiation-resistant logic. Basically, I think it included some form of multi-bit ECC at every stage of computation, and would repeat the operation as many times as necessary until the check succeeded. This made computation non-deterministic in time, but at least you eventually got the right answer.

 

[Amdlova]

Don't worry about wear some amd chips do that now. My poor 5700g died after seven months (he Don't die just become unstable and locking up windows). My be the new generations will wear and tears faster than before

 

[bit_user]

Don't worry about wear some amd chips do that now. My poor 5700g died after seven months (he Don't die just become unstable and locking up windows).

Somehow, I think you could manage to break just about anything with the letters "AMD" written on it.

 

[elforeign]

That's backwards-looking. If you look at the roadmaps in this article, they're talking about shrinking down to atomic structures. I think you can't assume CPUs and GPUs will always be so resilient. These chips could become much more of a "consumable resource" than how we're used to thinking of them.

Just look at what's happened with NAND and now even DRAM! The higher the density gets, the more dependent they're becoming on error-correcting technologies to make them work reliably.

You are absolutely correct; I wasn't thinking about it on a forward-looking basis. It's clear the closer we get to the physical limitations of current passing through smaller and smaller structures the stresses and inefficiencies will surely create trade-offs with respect to longevity unless some new materials are developed that can move us past silicon.

We've already seen the issues Intel had with that the past 7 years, interesting to see any updated deep dives or research into new materials.

 

[PlaneInTheSky]

 

[jp7189]

I ran various Intel/AMD chips 24/7 running 100% utilization and overclocked for years on end on BOINC. No chips ever failed or caused issues. I'm convinced it's pretty hard to "wear a chip out" unless the user really doesn't know what they're doing or for those niche cases of overclockers really pushing the physical boundaries of the chip design with exotic cooling.

Part of Intel's recent scaling and power woes was their insistence on using cobalt based interconnects because they said pure copper didn't meet their 10 year durability benchmark. Whereas TSMC had no such qualms. I wonder if there's someone out there that tracks semiconductor longevity to know if it's really a practical concern.

In any case, my takeaway is Intel is worried about the durability of smaller nodes.

 

[Bandit.masked]

This article would benefit from fewer advertisements. The ads have crashed Apple WebKit 6 times necessitating reloads.

 

[bit_user]

Wow, I finally made it through all the slides. If you want a good idea of where the industry is headed, over the next decade, you should really take a close look.

Also, I was poking around some other sites, to see what they think of this roadmap, and I happened upon this call for the USA to form its own equivalent to IMEC (among many other things):

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https://www.semianalysis.com/p/why-america-will-lose-semiconductors​

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I'm not really clear on the disadvantage of IMEC being European, unless the theory is that it's needed to feed and support semiconductor development from the professional and academic side.

Anyway, I'm not sure it's covering the same roadmap update, but they did reference IMEC's roadmap in a deep dive on the history and future of transistor design. Well out of my depth.

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https://www.semianalysis.com/p/the-future-of-the-transistor​

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[elforeign]

Wow, I finally made it through all the slides. If you want a good idea of where the industry is headed, over the next decade, you should really take a close look.

Also, I was poking around some other sites, to see what they think of this roadmap, and I happened upon this call for the USA to form its own equivalent to IMEC (among many other things):

​

https://www.semianalysis.com/p/why-america-will-lose-semiconductors​

​

I'm not really clear on the disadvantage of IMEC being European, unless the theory is that it's needed to feed and support semiconductor development from the professional and academic side.

Anyway, I'm not sure it's covering the same roadmap update, but they did reference IMEC's roadmap in a deep dive on the history and future of transistor design. Well out of my depth.

​

https://www.semianalysis.com/p/the-future-of-the-transistor​

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excellent, this is just what I was hoping for! Thanks