News Intel 14nm Rocket Lake-S Leaked: New Core Architecture, Xe Graphics, PCIe 4.0

[Admin]

Intel's last 14nm desktop CPU, Rocket Lake-S, will have big changes according to a new leak. It will feature a new core architecture, Xe graphics, PCIe 4.0 support, twice the DMI 3.0 bandwidth and Thunderbolt 4.

Intel 14nm Rocket Lake-S Leaked: New Core Architecture, Xe Graphics, PCIe 4.0 : Read more

 

[tiggers97]

"leak" is right. Why are the words saying PCIe 4.0, but the graphics in the middle show PCIe 3.0?

I wonder if Intel knows 10th gen is a dude, released at least 18 months after 9th gen and is not close to 11th gen being ready. Never mind it still won't be competitive with Zen 2, nor the upcoming Zen 3. And so they are starting to get the market warmed up for 11th gen.

 

[twotwotwo]

Good to see AV1 and PCIe 4--both really useful technologies that deserve to be more mainstream, and Intel hardware support should help them get there. If it's real-time AV1 encode it's a particularly big deal because software encode takes a ton of horsepower.

Also, you have to wonder how much will come out on time (from any vendor) given the pandemic. Delays are for the best; obviously lives matter more than ship dates. Just not reading any timetables the same these days.

 

[PaulAlcorn]

"leak" is right. Why are the words saying PCIe 4.0, but the graphics in the middle show PCIe 3.0?

I wonder if Intel knows 10th gen is a dude, released at least 18 months after 9th gen and is not close to 11th gen being ready. Never mind it still won't be competitive with Zen 2, nor the upcoming Zen 3. And so they are starting to get the market warmed up for 11th gen.

PCIe 4 off the CPU, PCIe 3 off the chipset. Tracks well with our previous reporting that Intel had issues implementing PCIe 4.0 in the chipset for Socket 1200 boards (both Comet and Rocket use LGA1200) https://www.tomshardware.com/news/i...lans-then-nixes-pcie-40-support-on-comet-lake

 

[bit_user]

"leak" is right. Why are the words saying PCIe 4.0, but the graphics in the middle show PCIe 3.0?

The slide shows PCIe 3.0 only on the chipset-connected lanes.

The PCIe coming directly off the CPU doesn't stipulate which generation, but then the boxes on the side say it's 4.0.

 

[bit_user]

PCIe 4 off the CPU, PCIe 3 off the chipset. Tracks well with our previous reporting that Intel had issues implementing PCIe 4.0 in the chipset for Socket 1200 boards

Ironically, the best argument for PCIe 4.0 would be to double the speed of the DMI link without increasing lane count (and therefore pin-count and cost). In fact, I thought Intel might even do that while keeping the graphics link @ 3.0. Intel went the exact opposite direction, however.

This is entirely independent of what flavor the chipset-connected lanes are. I mean, they already doubled DMI bandwidth while keeping the chipset-connected lanes at 3.0. They could've just done it another, possibly cheaper way.

 

[bit_user]

This sounds like water-cooling could be mandatory. Large dies will probably also make it fairly pricey.

 

[yeeeeman]

Not really. Skylake is so hot because it runs at crazy frequencies. I invite you to run a 9900K at 3.6-3.8Ghz and you'll be surprised it can fit in 95W TDP. If this is based on Tigerlake and brings a big IPC boost (25-30%) then they can run it at 4Ghz with 8 cores with reasonable TDP (105-125W), which is decent given 14nm.

 

[cryoburner]

Purportedly coming late this year on the 500-series platform...

That seems rather unlikely, especially seeing as a leaked roadmap from last year suggested Rocket Lake would be releasing in Q2 of 2021, more than a year from now. Seeing as Comet Lake still doesn't even have a release date, but was slated for Q2 of this year, I can't see Intel releasing its successor only months later, at least not on the desktop. Spring of next year, if not later, seems a lot more realistic.

 

[st379]

Not really. Skylake is so hot because it runs at crazy frequencies. I invite you to run a 9900K at 3.6-3.8Ghz and you'll be surprised it can fit in 95W TDP. If this is based on Tigerlake and brings a big IPC boost (25-30%) then they can run it at 4Ghz with 8 cores with reasonable TDP (105-125W), which is decent given 14nm.

25-30% IPC increase on 14nm+++++++++++++++++++++.... I doubt that.

 

[mdd1963]

Intel's last 14nm desktop CPU, Rocket Lake-S, will have big changes according to a new leak. It will feature a new core architecture, Xe graphics, PCIe 4.0 support, twice the DMI 3.0 bandwidth and Thunderbolt 4.

Intel 14nm Rocket Lake-S Leaked: New Core Architecture, Xe Graphics, PCIe 4.0 : Read more

......more 14nm+++++++++ nonsense?

Keep it...

 

[spongiemaster]

If this leak is even remotely true, what's the point of comet lake? Unless you REALLY want a mainstream 10 core CPU from Intel, it makes no sense. Intel is struggling to get Skylake 4 out the door and now they are supposed to release Rocket Lake less than 6 months later? There's no way Rocket Lake is getting released before the end of the year, even if there was no Covid-19. If the spec leaks are all legit, Rocket Lake looks like the first mainstream Intel CPU to actually look forward to since Skylake 1.0. Which ended up not being that exciting compared to Broadwe...well Haswell really, once it was released.

 

[Chung Leong]

Does "CPU attached Storage" translate to support for Optane DCPMM? It'd be nice to see that tech finally coming to the customer space.

 

[bit_user]

If this is based on Tigerlake and brings a big IPC boost (25-30%) then they can run it at 4Ghz with 8 cores with reasonable TDP (105-125W), which is decent given 14nm.

Do you really think they're going to clock it at just 4 GHz? I don't.

 

[bit_user]

Seeing as Comet Lake still doesn't even have a release date, but was slated for Q2 of this year, I can't see Intel releasing its successor only months later, at least not on the desktop. Spring of next year, if not later, seems a lot more realistic.

Remember Broadwell? Their desktop platform basically skipped it and went straight to Skylake. They could surprise us, and do it again. They're certainly desperate enough, and Comet Lake's rumored power consumption could be causing them quite some consternation.

Especially if they're facing supply-side delays getting Comet Lake out, they might just view it as an opportunity to skip ahead.

 

[bit_user]

25-30% IPC increase on 14nm+++++++++++++++++++++.... I doubt that.

It's possible, but only if they drop clock speed by a lot.

Or, maybe that's just using some benchmarks optimized for AVX-512... either way, something doesn't smell right. I don't think there's a lot more performance in 14 nm than what we've been seeing.

 

[bit_user]

Does "CPU attached Storage" translate to support for Optane DCPMM? It'd be nice to see that tech finally coming to the customer space.

The block diagram shows 2-channel DDR4 memory and no other CPU-direct storage connections besides PCIe 4.0 x4. But, the chipset shows "Intel Optane Memory" hanging off a PCIe 3.0 x4 link.

Either way, it doesn't look like you get your Optane DIMMs.

The block diagram is much easier to read, if you right-click it and view in another tab. Then, you can more easily zoom it.

 

[spongiemaster]

Do you really think they're going to clock it at just 4 GHz? I don't.

I would be surprised if base clocks were that high. I think the 9900KS is the only CPU with a 4Ghz base clock. With a 25% IPC gain, a Rocket Lake CPU with a 4Ghz base clock would perform like a 5Ghz Coffee Lake while being able to stay within the actual stated 127W TDP. For OEM's that stick to the TDP, that would be pretty decent. Sure, you can blow past the TDP with turbo and overclocking, but you wouldn't have to. Lower core count boosts would result in performance not possible with any current CPU, while also not having to go nuclear on the power side.

 

[bit_user]

Sure, you can blow past the TDP with turbo and overclocking, but you wouldn't have to.

Well, @InvalidError should probably chime in here, but you don't just get more IPC for free. Usually, it involves some significant increases in critical path length, which can be offset with a smaller node. If you don't also move to a smaller node, then it hurts your timing and you end up with a lower ceiling on your clock speed, no matter how much power you're willing to burn.

Only time will tell, but I highly doubt they just pulled a true 25% IPC gain out of nowhere. There's definitely a catch, of some sort. Either it's not nearly that much, in typical usage, or it's really going to hurt clock speeds to the point of maybe nullifying the net-gains, which would be pointless.

 

[TerryLaze]

Well, @InvalidError should probably chime in here, but you don't just get more IPC for free. Usually, it involves some significant increases in critical path length, which can be offset with a smaller node. If you don't also move to a smaller node, then it hurts your timing and you end up with a lower ceiling on your clock speed, no matter how much power you're willing to burn.

Only time will tell, but I highly doubt they just pulled a true 25% IPC gain out of nowhere. There's definitely a catch, of some sort. Either it's not nearly that much, in typical usage, or it's really going to hurt clock speeds to the point of maybe nullifying the net-gains, which would be pointless.

This isn't about IPC as we knew it in the past, this is about benchmarks.
"With Sunny Cove, Intel is also for the first time focusing on more parallelization. Instead of four, there are now five allocators and 10 instead of 8 ports for the arithmetic units."
You get 25% more allocators and 25% more ports and that will show in benchmarks.According to what we have seen with sunny cove 25% more units got them about 18% better results in multithreading benchmarks.

You don't need to change any path length you don't get any influence on possible clocks and no nothing,you just get faster in DC/workstation loads without any negatives except if you count the core size as a negative.
You will have to power more hardware so the power draw will possibly be even higher but especially for desktop who cares?! If the performance is there power draw is secondary.
Size and power is probably also the reason that the leaks are talking about 8cores now,which would also make sense for intel because they could then release the 10core version as 11gen.
https://www.pcbuildersclub.com/en/2...ice-lake-with-multi-chip-design-and-more-ipc/

 

[st379]

It's possible, but only if they drop clock speed by a lot.

Or, maybe that's just using some benchmarks optimized for AVX-512... either way, something doesn't smell right. I don't think there's a lot more performance in 14 nm than what we've been seeing.

There was another rumor about big.little architecture coming to desktop.
It does not make any sense on desktop unless they want to maintain the "best gaming" crown.
With 4 very powerful cores, they could maintain there "legendary" 10 fps on ryzen 4000.
Lol sneaky Intel.

 

[MTEK-XKI]

"enhanced display capabilities with integrated HDMI 2.0b and DisplayPort 1.4a."

So HDMI 2.1 and DP 2.0 in.... 5-years, thereabouts?

 

[InvalidError]

Well, @InvalidError should probably chime in here, but you don't just get more IPC for free. Usually, it involves some significant increases in critical path length, which can be offset with a smaller node. If you don't also move to a smaller node, then it hurts your timing and you end up with a lower ceiling on your clock speed, no matter how much power you're willing to burn.

That's pretty much it. Increasing IPC practically always comes at the expense of increased circuit complexity and if the process' performance does not increase enough to absorb the increased complexity, you end up with lower clocks. If you look at Ice Lake mobile and compare them to Comet Lake mobile parts, Ice Lake clocks ~15% lower despite its 10nm advantage.

You don't need to change any path length you don't get any influence on possible clocks and no nothing,you just get faster in DC/workstation loads without any negatives except if you count the core size as a negative.

Do you really think that making the execution back-end 25% wider has no effect on the complexity (critical path lengths) of everything upstream responsible for feeding that extra parallelism and everything downstream responsible for resolving the outcomes of speculative execution? Intel doubled the re-order buffer depth in Ice Lake, that does not come for free. Ice Lake mobile chips fall ~15% short of Comet Lake clocks despite their 10nm advantage for a reason: 10nm isn't fast enough to offset the increased complexity.

 

[spongiemaster]

Well, @InvalidError should probably chime in here, but you don't just get more IPC for free. Usually, it involves some significant increases in critical path length, which can be offset with a smaller node. If you don't also move to a smaller node, then it hurts your timing and you end up with a lower ceiling on your clock speed, no matter how much power you're willing to burn.

Only time will tell, but I highly doubt they just pulled a true 25% IPC gain out of nowhere. There's definitely a catch, of some sort. Either it's not nearly that much, in typical usage, or it's really going to hurt clock speeds to the point of maybe nullifying the net-gains, which would be pointless.

Kick it old school and read a Conroe review comparing it to previous generation Pressler. Both 65nm, Conroe with much lower clock speeds and power usage, and it still crushed Pressler across the board.

25% IPC improvement is probably optimistic, however, we are looking at two architectural generations forward and by the time this releases likely next year, we're looking at almost 6 years of Skylake. You don't have to believe in unicorns and leprechauns to think 15-20% should be possible. We'll certainly have a better idea when mobile Tiger Lake releases this summer.

 

[TerryLaze]

Do you really think that making the execution back-end 25% wider has no effect on the complexity (critical path lengths) of everything upstream responsible for feeding that extra parallelism and everything downstream responsible for resolving the outcomes of speculative execution?

What you are talking about is the amount of instructions you can get when running all sorts of different things.

I'm talking about specific benchmarks that don't need any kind of upstream or downstream complexity,that you can just feed all the instructions into the CPU and the output needs no sorting.
In 7zip for example they state a 75% increase,and that's because now it fits into cache and there is no complexity to it, the software just sends as many instructions to the CPU as the CPU can handle and the output is just the MIPS.
"The strong increase can also be seen in a demonstration with 7-Zip, in which an Ice Lake prototype calculated 75 percent faster than its predecessor. "