News Intel Announces 288-Core Processor, 5th-Gen Xeon Arrives December 14

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bit_user

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Edit: Correction noted. Thanks!
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Here's the remaining informational content of my post, in case anyone missed it:

Emerald Rapids is built on Intel 7. Likely the same iteration of it that was used for Raptor Lake. Granite Rapids and Sierra Forest are using Intel 3. They're the first announced products to use it.

@PaulAlcorn , as usual, thanks for your excellent coverage!
: )
 
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bit_user

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"Moore's law is dead!" yee
On that front, it's more instructive to look at the announced roadmaps of IFS, TSMC, and Samsung. They tell you what improvements on density, power, and performance to expect. You needn't wait for actual product announcements to see what those nodes can do.

The power & performance metrics are somewhat artificial, because they presume the exact same microarchitecture. So, treat them as a lower bound, in terms of performance and efficiency, and an upper bound on density.

And, for a really long-range view (but without specific performance metrics), you should look to IMEC:
 
Sep 13, 2023
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On that front, it's more instructive to look at the announced roadmaps of IFS, TSMC, and Samsung. They tell you what improvements on density, power, and performance to expect. You needn't wait for actual product announcements to see what those nodes can do.

The power & performance metrics are somewhat artificial, because they presume the exact same microarchitecture. So, treat them as a lower bound, in terms of performance and efficiency, and an upper bound on density.

And, for a really long-range view (but without specific performance metrics), you should look to IMEC:

I am picking up info - piece by piece. I am currently not looking up specific news about hardware. I just came across this announcement and thought "Oh well, people on the net used to say "moore's law is dead"" but then again it is just my own ignorance to talk before making comprehensive research. Anyway, I appreciate your time - have a good one
 

bit_user

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I am picking up info - piece by piece. I am currently not looking up specific news about hardware. I just came across this announcement and thought "Oh well, people on the net used to say "moore's law is dead"" but then again it is just my own ignorance to talk before making comprehensive research. Anyway, I appreciate your time - have a good one
What worries me is the cost of new nodes. What I think we're likely to see is more of a "fizzling out", rather than smacking hard into a wall, due to increasing cost of new nodes, while the returns diminish.

They touched on this more, in a slightly earlier IMEC article:
2JbFA4fuuvxdHiPdveKZ5.jpg

Also, this (though, getting a bit dated):
main-qimg-81fb704374c332ad5c5e27e11cbd4ac5-lq

If anyone finds a plot with newer nodes, please share!


Oh, and SRAM scaling has essentially stopped. Perhaps more exotic, multi-layer cell designs will achieve better areal density. But, to the above point, that won't come without additional cost.
 

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What worries me is the cost of new nodes. What I think we're likely to see is more of a "fizzling out", rather than smacking hard into a wall, due to increasing cost of new nodes, while the returns diminish.
And hence the rapid adoption of advance packaging with full chip disaggregation. enabling utilization of advance node only where it shows ROI benefit.
 
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bit_user

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How do Intels high e-core chips compare to the high arm core count chips?
We don't know, yet. Sierra Forest isn't due out until mid-2024 and will use the Crestmont mircroarchitecture on Intel 3. So, there are way too many variables to form a reasonable extrapolation from the data we have on the current low core-count Gracemont CPUs using Intel 7.

I should add that Xeons tend to sample a lot sooner than consumer CPUs - possibly up to a year, in advance. So, I wouldn't be surprised if there are already (or soon to be) some engineering samples floating around, with the inevitable benchmark leaks soon to follow.
 
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And hence the rapid adoption of advance packaging with full chip disaggregation. enabling utilization of advance node only where it shows ROI benefit.
Yeah, but if you just look at that delidded 288-core CPU, the majority of the die area is still very much in the compute dies, which are made on the most advanced node. No doubt the chiplets & mixed-node thing helps, but it's not a panacea.

Yes, chiplets still help with improving yield, but each die-hop is energy-intensive, so you don't want to get carried away. That's probably why their compute dies are each 578 mm^2, which is non-trivial even on current, mature nodes.
 
What worries me is the cost of new nodes. What I think we're likely to see is more of a "fizzling out", rather than smacking hard into a wall, due to increasing cost of new nodes, while the returns diminish.
Intel is in a unique position moving from Intel 7 to Intel 4/3 where the overall cost will likely go down. I'd imagine that the move to 20a/18a will probably erase all of those gains however given all the new manufacturing technologies being applied.

I certainly agree that given the increased use of multipatterning and delays with High-NA EUV machines everyone is going to slow down even if new tech is available.
 

bit_user

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5th-Gen Xeon by which calendar?
Xeon processors started on 1998
You make a good point. The headline took a shortcut, but is referring to 5th gen "Scalable" series Xeon processors. The "Scalable" series started with Skylake, which was the first to use a mesh-based interconnect fabric (apart from Xeon Phi, that is). It was also the first to reach 28 cores (Broadwell Xeons topped out at 22 cores) and moved to 6-channel memory, up from 4-channel.

The shift in naming also coincided with a change from the "EP" designation to "SP". I believe it's meant to stand for "Scalable Platform". Here's when it was first announced:
 
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