Has anyone looked at whether Intel 7 provides more density than their 10 nm SF node, whether Intel 3 provides better density over Intel 4, or whether Intel 18A provides better density over Intel 20A?
I have a suspicion that Intel 7 is really just Intel 10+++, Intel 3 would've previously been called Intel 4+, and that the Intel of old would've just said Intel 18A was Intel 20A+.
Regardless of what they call them, it's good to see Intel's process nodes improving. I just think what they accomplished is probably a little less miraculous than it sounds. Especially, considering how underwhelming Meteor Lake has been, performance-wise.
Both 10nm SF and Intel 7 has larger pitches than predecessors, so theoretical maximum density goes down. However, they aren't taking full advantage of it due to their obsession of clocks, so in reality there's no difference.
While on paper Intel 3 is a revision of Intel 4, in reality Intel 3 brings in HD libraries, increase in density for HP libraries, and other libraries that allow a full SoC, while Intel 4 is basically only for CPU. Same is true with 20A vs 18A. 18A is the real, full node while 20A exists purely for bringing 18A reliably.
Meteorlake has been plagued with delays, which is part of the disappointment. Also it looks like Intel 4 might be at fault too because again, it's a stepping stone for Intel 3, which will be utilized fully. Same should be with 20A.
It isn't completely correct to call 10nm SF, Intel 7, and 3 just mere plusses either. They bring a rather big gain in transistor performance. The 14nm plusses only brought 3-5% gains, while 10nm SF alone brought 4x 14nm plus worth of gains.
Intel 3 brings a 18% transistor performance gain, so again it's significant. Intel 4 brings 20%, so Intel 3 in terms of performance is practically a new node. Intel 7 brought 10-15% gains.
https://www.anandtech.com/show/1682...nm-3nm-20a-18a-packaging-foundry-emib-foveros
(That's also ignoring the point I made above, that Intel 4/20A seriously lacks libraries to make anything other than CPU tile, no memory controllers, IO, or SoC)