News Intel Bartlett Lake CPUs power new 120 x 160mm COM-HPC modules from congatec — features up to 24 hybrid cores, 128GB of DDR5-4000 memory, and 32 EUs

[Admin]

Bartlett Lake-S is here, though in a hybrid configuration and only for NEX applications.

Intel Bartlett Lake CPUs power new 120 x 160mm COM-HPC modules from congatec — features up to 24 hybrid cores, 128GB of DDR5-4000 memory, and 32 EUs : Read more

 

[bit_user]

So where is the P-core-only Bartlett Lake-S? Rumors suggest that these processors are slated for Q3 2025, with the Core 9 SKUs allegedly offering 12 full-fat performance. Similar to their predecessors, these CPUs should employ Raptor Cove P-cores, so there won't be major improvements in IPC or efficiency.

If Intel wanted to make some waves, they could enable AVX-512 on them. At least on the Xeon E-branded ones.

I'm not saying it's likely, as it would mess with their whole messaging around the subject, but it would be a cheap way they could add further value. Especially if it's limited to just the Xeon-branded models, I don't think the potential "market confusion" would be a major issue.

I wonder if their original plan for the Xeon E-2400 series was to do that, but either they found some bug in the implementation or had a last-minute change-of-heart. Because, it's otherwise a little suspicious that all of those models have their E-cores disabled.

 

[thestryker]

If Intel wanted to make some waves, they could enable AVX-512 on them. At least on the Xeon E-branded ones.

I think this would be the only logical reason for the P-core only part to exist.

It doesn't really make sense to me that they'd design a new die just for people who wanted client class 10 and 12 P-core parts. They also don't need it to keep the DUV lines open because RPL already does that.

 

[bit_user]

I think this would be the only logical reason for the P-core only part to exist.

Eh, their story about it being for some sort of communications vertical does sort of align with having symmetric cores. I'm sure something like an RTOS would hate hybrid CPUs. They almost certainly disable SMT, as well.

I thought the 12x P-core part was just a hedge against Arrow Lake being late or regressing on gaming performance. The leaked launch launch timing doesn't tally with that, but maybe they pushed it back or it hit its own unplanned delays.

There is that other theory about it being offered as an upgrade for people with LGA 1700 boards, who maybe still have Alder Lake.

It might not be only one of these reasons.

 

[thestryker]

Eh, their story about it being for some sort of communications vertical does sort of align with having symmetric cores. I'm sure something like an RTOS would hate hybrid CPUs. They almost certainly disable SMT, as well.

Intel already sells the Xeon E with disabled IGP/E-cores so the only advantage should be the higher core count.

I thought the 12x P-core part was just a hedge against Arrow Lake being late or regressing on gaming performance. The leaked launch launch timing doesn't tally with that, but maybe they pushed it back or it hit its own unplanned delays.

There is that other theory about it being offered as an upgrade for people with LGA 1700 boards, who maybe still have Alder Lake.

It might not be only one of these reasons.

A 12 P-core part shouldn't be faster at pretty much anything when compared to a 14900K. They certainly didn't make the decision to design it after they figured out the issues with RPL given how far back the rumors go.

That's why I don't understand the new die unless it enables something that the current RPL doesn't.