News Intel Demoes 8-Core, 528-Thread PUMA Chip with 1 TB/s Silicon Photonics

[Admin]

Intel demoed a non-x86 chip with eight cores, 528 threads, and 1TB/s of optical I/O at Hot Chips 2023.

Intel Demoes 8-Core, 528-Thread PUMA Chip with 1 TB/s Silicon Photonics : Read more

 

[Kamen Rider Blade]

What I'm more surprised is that Intel didn't do this on their own internal fabs.

Why did they need to use TSMC for this?

Also, a "Custom RISC" architecture vs a derivative off of x86, hmmm.

 

[InvalidError]

Also, a "Custom RISC" architecture vs a derivative off of x86, hmmm.

If you are going to build an application-specific (graph analysis) CPU with 66 hardware threads per core, you likely don't want a complex instruction decoder bottlenecking the whole thing and adding a handful of cycles latency penalty to every branch prediction miss and every hardware thread switch.

Kind of a similar story to CPU vs GPU cores.

66 threads is an odd number to settle on. Must have barely missed mandatory performance targets with 64.

 

[NeoMorpheus]

Also, a "Custom RISC" architecture vs a derivative off of x86, hmmm.

And you can bet that the number one "feature" would be the IP not accessible to AMD, hence they finally found a way to kill their x86 license agreement.

Itanium lives once more!

 

[Eximo]

Intel's best process nodes are busy churning out Intel x86 chips for the consumer computer market or doing development directly related to it. Makes so sense to interrupt their production to make a demo chip. They probably also have some spare TSMC fab time allotted.

 

[dehjomz]

So what OS/software can this custom chip run? Also, is Intel signaling the end of x86 and the dawn of some new RISC-based architecture ?

 

[Kamen Rider Blade]

If you are going to build an application-specific (graph analysis) CPU with 66 hardware threads per core, you likely don't want a complex instruction decoder bottlenecking the whole thing and adding a handful of cycles latency penalty to every branch prediction miss and every hardware thread switch.

Kind of a similar story to CPU vs GPU cores.

66 threads is an odd number to settle on. Must have barely missed mandatory performance targets with 64.

They couldn't have killed 2x threads per core and added in 2x more cores for 10x core?

 

[Kamen Rider Blade]

And you can bet that the number one "feature" would be the IP not accessible to AMD, hence they finally found a way to kill their x86 license agreement.

Itanium lives once more!

May the "Itanium 2" sink like the original "Itanic!"

 

[JamesJones44]

So what OS/software can this custom chip run? Also, is Intel signaling the end of x86 and the dawn of some new RISC-based architecture ?

There are plenty of Linux variants out there that can run on RISC-V and other RISC variants. My guess would be a fork of one of those variants with updated kernels to handle the custom instructions. I also wouldn't be surprised if Intel's "custom"-RISC instructions where forked from another source.

 

[InvalidError]

So what OS/software can this custom chip run? Also, is Intel signaling the end of x86 and the dawn of some new RISC-based architecture ?

Since it is basically a tech-demo for graph analytics and on-package photonics, it may very well be running some sort of bare-bones micro-kernel just to coordinate compute and IO scheduling across nodes and with the host system/OS.

The way I read it, these things are fundamentally meshed memory controllers with distributed compute capabilities, not stand-alone devices.

 

[NeoMorpheus]

May the "Itanium 2" sink like the original "Itanic!"

Fingers crossed that it takes intel with it! 🙂

 

[TerryLaze]

What I'm more surprised is that Intel didn't do this on their own internal fabs.

Why did they need to use TSMC for this?

Also, a "Custom RISC" architecture vs a derivative off of x86, hmmm.

Because this was about the interconnect and not about the CPU, they just needed anything that could push 1TB/s through the interconnect.
If intel can mature this tech they will start using it in their normal x86 server lineup.

Intel unveiled its first direct mesh-to-mesh photonic fabric at the Hot Chips 2023 chip conference, highlighting its progress towards a future of optical chip-to-chip interconnects that are also championed by the likes of Nvidia and Ayar Labs.

 

[Order 66]

Fingers crossed that it takes intel with it!

goodbye competition to AMD if that happens. AMD will then become complacent like Intel did and pull a 14nm++++ type situation just like Intel

 

[expunged]

What I'm more surprised is that Intel didn't do this on their own internal fabs.

Why did they need to use TSMC for this?

Also, a "Custom RISC" architecture vs a derivative off of x86, hmmm.

because intel fabs are still at 10nm TSMC is at 5nm. I doubt intel will make its mark with their 1.8nm chip due 2024.

 

[Kamen Rider Blade]

If intel can mature this tech they will start using it in their normal x86 server lineup.

Since TSMC is making this chip, I'm sure TSMC will have their own flavor of Silicon Photonics that AMD will also use.

 

[NeoMorpheus]

goodbye competition to AMD if that happens. AMD will then become complacent like Intel did and pull a 14nm++++ type situation just like Intel

Counting on it, so that will make ARM, RISC-V, OpenPOWER and whoever else pick up the torch and fight the new evil AMD!

I just dont want Intel on top, because we know how it will go.

 

[palladin9479]

Really wanted to make a Crysis joke here...
I love stuff like this, though it's way outside the consumer and enterprise IT space. You would use stuff like this when building a super computer or some sort of custom processing center that requires insane low latency point to point bandwidth.

What I'm more surprised is that Intel didn't do this on their own internal fabs.

Why did they need to use TSMC for this?

Also, a "Custom RISC" architecture vs a derivative off of x86, hmmm.

As others have said, TSMC currently has the most advanced EUVL technology on the planet, followed by Samsung with Intel a distant third, though they are burning hard to catch up. Since these devices are designed to be used in a giant multi-node optical network for massive parallelism, using legacy x86 makes no sense when RISC is much easier to scale horizontally.

 

[JamesJones44]

Counting on it, so that will make ARM, RISC-V, OpenPOWER and whoever else pick up the torch and fight the new evil AMD!

I just dont want Intel on top, because we know how it will go.

If everything switched to RISC-V/ARM you wouldn't have to worry about it. There would be tons of competition.

 

[DonQuixoteIII]

@Paul Acorn - "The eight cores, which consume 1.2 billion transistors," Maybe 'utilize' instead of 'consume'. Or'comprise'.... Consume is just plain wrong.

 

[bit_user]

Surprisingly for an x86-centric company like Intel, the test chip utilizes a custom RISC architecture

That's nothing new. > 15 years ago, they made an early forerunner of Xeon Phi, using RISC cores:

​

Our Manycore Future

As we look into the future of computing, massively parallel processing seems destined to become the dominant model. How this transition is going to occur is the subject of much controversy. Editor Michael Feldman takes a look at a recent report on parallel computing and offers some perspective...

www.hpcwire.com

​

Intel even sold custom-designed RISC CPUs, in its deep past. Two of these:

• https://en.wikipedia.org/wiki/Intel_i860
• https://en.wikipedia.org/wiki/Intel_i960

These days, they have plenty of non-x86 products, such as their GPUs and Habana Labs' AI chips. Even the VPU embedded in their upcoming Meteor Lake is non-x86.

 

[bobdvb]

Interesting that they called it PUMA, because Intel already had a product called Puma which was DOCSIS cable chips for cable modems. They sold the business unit in 2020 for $150m.
Short memories at Intel?

 

[ekio]

Of course it’s not x86!
x86 is a pile of sh!t that even intel is stuck with because it’s hard to move an ecosystem to a different ISA. (That’s why risvc really needs to win the next battle because that will benefit everyone for a long time both for quality and open competition).
If you want efficiency, you want to avoid x86 at all price, even intel. And they probably went with a riscv like with even less instructions to start. Now we want the flops in float32 to measure the perfs

 

[dalauder]

Not impressed. They said "400ns" latency.

Threadripper has been doing 200GB/s on 15ns latency for like 5 years. You can accomplish any task this system could do (even if it COULD run Windows and normal software) faster with a cheaper dual-Threadripper system, which could have up to 256 threads.

This is an interesting proof-of-concept with optical interconnects, but it's not worth much at all in terms of tech specs.

EDIT: I'm now aware that my comparison was invalid. Is this is more like a replacement for networking, data, or USB cables then?

 

[TerryLaze]

Since TSMC is making this chip, I'm sure TSMC will have their own flavor of Silicon Photonics that AMD will also use.

The chip and the interconnect are completely different things.
Just because intel bought an chip from TSMC didn't make TSMC magically own the right to use intel's IP for the interconnect.
That's like saying that TSMC can legally sell ryzen CPUs, that they made on the side, as TSMC branded CPUs.

Not impressed. They said "400ns" latency.

Threadripper has been doing 200GB/s on 15ns latency for like 5 years. You can accomplish any task this system could do (even if it COULD run Windows and normal software) faster with a cheaper dual-Threadripper system, which could have up to 256 threads.

This is an interesting proof-of-concept with optical interconnects, but it's not worth much at all in terms of tech specs.

And how close is 200Gb/s to 1Tb/s ?
This tech will connect multiple racks with each rack having multiple sockets.
Having 400ns, basically from one "computer" to the next, is pretty good.

 

[edzieba]

Since TSMC is making this chip, I'm sure TSMC will have their own flavor of Silicon Photonics that AMD will also use.

The chip is not manufactured by TSMC. The central die is fabbed by TSMC, but the Silicon Photonics dies are fabbed by Intel, and the chip is packaged by Intel (hence why it using EMIB bridges, not InFO-L or CoWoS-L).

Not impressed. They said "400ns" latency.

Threadripper has been doing 200GB/s on 15ns latency for like 5 years

Between dies in a single package. The entire point of this chip is to demo interconnects between packages in different racks.
It makes about as much sense as complaining that a 100m 10Gb/s ethernet connection is unimpressive because DDR5 is 50GB/s.