News Intel details next-gen 18A fab tech: significantly more performance, lower power, higher density

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So, how do these gains compare against the predictions and prior information? We always knew 18A would be better than Intel 3, but is Intel on-target?

Another key question, and one we aren't likely to get insight into for a while, is what happens when you remove PowerVia/BSPDN. I believe we previously heard that it adds non-trivial cost, and therefore it's likely some customers will opt to forego it. How competitive is 18A, without it? How do 18A's costs compare to TSMC, with it?
 
So, how do these gains compare against the predictions and prior information? We always knew 18A would be better than Intel 3, but is Intel on-target?

Another key question, and one we aren't likely to get insight into for a while, is what happens when you remove PowerVia/BSPDN. I believe we previously heard that it adds non-trivial cost, and therefore it's likely some customers will opt to forego it. How competitive is 18A, without it? How do 18A's costs compare to TSMC, with it?
I still think that's TBD info
 
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Nonetheless, for Intel it is crucial to show that it can develop a competitive node and ramp it to high volume, so 18A will play a vital role for the future of Intel's foundry business.
I suspect a limited number of EUV machine deliveries held Intel back from wider production of Intel 4/3. When 18A launches Intel will have had two more years to install EUV machines and even today Intel is avoiding more products on Intel 3, probably to divert resources to 18A. So if yields are comparable it ought to reach a far greater volume than Intel 4 & 3 did.
 
even today Intel is avoiding more products on Intel 3, probably to divert resources to 18A.
Intel quietly moved MTL over to Intel 3 with the Core 200 launch and all Intel 3/4 (though I assume they've wound down 4) production is in Ireland. All production at Fab 52 in Arizona will be 18A with Oregon being the other 18A production source. This gives them quite a bit of production flexibility, but I have no doubt they're still paying the price for being so late on EUV.
 
still have to see yield rate, if produce 100 wafers but 80 wafers are failed, it is still be considered fail, although that 20 wafers are very powerful.
 
still have to see yield rate, if produce 100 wafers but 80 wafers are failed, it is still be considered fail, although that 20 wafers are very powerful.
well, if 80% of the die from a wafer are good, I'm guessing Intel products will start moving to their own fabs.

They have already said that their yields are appropriate at this stage in the development ... or, at least PG said that. MJH has given it her vote of approval by scheduling the Panther Lake ramp there, with Clearwater Forest also cleared to go, now that its hybrid bonding issue has been resolved.
 
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well, if 80% of the die from a wafer are good, I'm guessing Intel products will start moving to their own fabs.
https://www.techpowerup.com/329613/intel-18a-yields-are-actually-okay-and-the-math-checks-out
It's much less than that, at least for big dies it's assumed to be around 50% ,but that's about the same as TSMC so they seem to be fine.

"If we assume that Intel has refined its 18A node more, we can conclude that even with some larger designs hitting the EUV machine reticle limit of 858 mm², Intel's yields could be hitting the 50% mark. If we assume that the best player TSMC achieves a 0.1 defect rate, yields of chips at 858 mm² size are barely above 50% using all available models. That is the fully functioning silicon die, of course"
 
I'm loving the positive news coming from the 18a development. Hopefully, it's true and not just a hype train for investors.

I do wonder about heat generation with BSPDN. Does it mean greater heat on the back of the chip where it's harder to cool?
 
I never really doubted this. Intel has had many problems. None of them were ever giving their technical people all of the resources and latest technology they needed to create cutting-edge chips. When management finally made the decision to go all-in and spend $600 million a couple of years ago (more since then) to be the first to get these newest EUV machines from ASML, I considered it a given that it would be a success.

It's still Intel, and they have been producing these chips since they've existed. No one knows more about this than Intel engineers and they haven't forgotten how to make microchips. I think the general public has confused mismanagement with a lack technical prowess. The Intel nerds are as good as anyone.
 
Well, this little party didn't last long.

No matter what the reason, it's certainly not good news. Don't yet know if it's truly a bad sign, but it's never a good sign to move something originally slated for 18A over to TSMC.
Intel 18a for Laptop and Server
TSMC 2nm for Desktop PC
??? for XE3 Celestial Discrete GPU
something like Intel 18a Yr 2026 total production output may not afford all production line demands.
 
Well, this little party didn't last long.

No matter what the reason, it's certainly not good news. Don't yet know if it's truly a bad sign, but it's never a good sign to move something originally slated for 18A over to TSMC.
Not knowing what their capacity may be or what, if any, customers they have for that process it's hard to tell. Just because they have this new node I can't imagine they have near the capacity of TSMC.
 
https://www.techpowerup.com/329613/intel-18a-yields-are-actually-okay-and-the-math-checks-out
It's much less than that, at least for big dies it's assumed to be around 50% ,but that's about the same as TSMC so they seem to be fine.

"If we assume that Intel has refined its 18A node more, we can conclude that even with some larger designs hitting the EUV machine reticle limit of 858 mm², Intel's yields could be hitting the 50% mark. If we assume that the best player TSMC achieves a 0.1 defect rate, yields of chips at 858 mm² size are barely above 50% using all available models. That is the fully functioning silicon die, of course"
The High-NA EUV Lithography machines used for Intel's 18a process halve the reticle limit. Multiple dies seems to be the only path now. I haven't read much about 'stitching' dice together to form larger chips, but alignment issues must be insanely problematic wrt good yields, if possible at all (if not, I'm all ears).
 
The High-NA EUV Lithography machines used for Intel's 18a process halve the reticle limit.
Intel isn't using their High-NA machines for 18A production (I'm assuming the test wafers have all been 18A though). These machines aren't scheduled to be put into production until 14A and I imagine that will depend on ASML to a degree since I don't believe they've shipped any production units yet (the 5000 wasn't intended as production).
 
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Well, this little party didn't last long.

No matter what the reason, it's certainly not good news. Don't yet know if it's truly a bad sign, but it's never a good sign to move something originally slated for 18A over to TSMC.
You go ahead and trust a random post on X.
Halo 18A by the time most people have the most money to spend.
https://www.intc.com/news-events/pr...-reports-first-quarter-2025-financial-results
  • Intel 18A is expected to ramp in the second half of 2025 to support the launch of Intel’s first Panther Lake SKU by year-end, with additional SKUs coming in the first half of 2026.