News Intel Details PowerVia Backside Power Delivery Technology

[Admin]

Intel reveals the benefits of backside power delivery networks and how it achieved it. This technology will be a major benefit for the upcoming 20A and 18A manufacturing nodes.

Intel Details PowerVia Backside Power Delivery Technology : Read more

 

[Metal Messiah.]

This new PowerVia backside power delivery concept and it's success can be attributed to Nano-TSVs which are five-hundred times smaller than typical TSVs, as compared to previous backside power delivery concepts. This also allowed Intel to relax the pitch of the critical M0 metal layer, enlarging it from 30 nm to 36 nm.

So these deliver power straight to the M0 layer where the processing actually happens rather than having to pass through the M0 layer. It also doesn't have to account for extra power routing mucking up the signaling above the M0 layer.

However, Intel doesn’t offer a more detailed explanation as to why constructing an E-core with PowerVia technology improved the maximum frequency (fMax) of the core by 6%, though, I suspect it has to do with a higher voltage actually reaching the transistors themselves, allowing them to clock a bit higher.

 

[Metal Messiah.]

BTW, IMEC have already demonstrated this tech back in 2021. They even illustrated the concept of moving power delivery networks to the backside of thinned wafers using nano-TSVs and BPR technology. So this isn't a new tech as Intel claims.

Imec demonstrates critical building blocks for a backside power delivery network | imec

In several papers presented at the 2021 Symposia on VLSI Technology and Circuits (VLSI 2021), imec reports progress in developing enabling technologies for a backside power delivery network. First, the impact of backside wafer processing on the performance of ‘frontside’ FinFET devices was...

www.imec-int.com

 

[I_draw_on_bald_heads]

This new PowerVia backside power delivery concept and it's success can be attributed to Nano-TSVs which are five-hundred times smaller than typical TSVs, as compared to previous backside power delivery concepts. This also allowed Intel to relax the pitch of the critical M0 metal layer, enlarging it from 30 nm to 36 nm.

So these deliver power straight to the M0 layer where the processing actually happens rather than having to pass through the M0 layer. It also doesn't have to account for extra power routing mucking up the signaling above the M0 layer.

However, Intel doesn’t offer a more detailed explanation as to why constructing an E-core with PowerVia technology improved the maximum frequency (fMax) of the core by 6%, though, I suspect it has to do with a higher voltage actually reaching the transistors themselves, allowing them to clock a bit higher.

The backside power delivery results in less voltage droop, which leads to less noise on the power supply to the clock drivers, which leads to less clock jitter and extra timing margin, which results in a higher fmax.

 

[thestryker]

While I'm glad the development has been successful I'm even happier that we're seeing Intel manufacturing minimizing delays by splitting up new technologies. It seems like a lot of the time companies don't learn the right lesson from a failure to deliver like the 10nm process was. Due to the extreme cost and timetables for EUV machines Intel needed something to differentiate as undercutting on cost just isn't really viable to grow IFS. It ought to be really interesting seeing what happens with 20/18A over the next two years.

BTW, IMEC have already demonstrated this tech back in 2021. They even illustrated the concept of moving power delivery networks to the backside of thinned wafers using nano-TSVs and BPR technology. So this isn't a new tech as Intel claims.

Imec demonstrates critical building blocks for a backside power delivery network | imec

In several papers presented at the 2021 Symposia on VLSI Technology and Circuits (VLSI 2021), imec reports progress in developing enabling technologies for a backside power delivery network. First, the impact of backside wafer processing on the performance of ‘frontside’ FinFET devices was...

www.imec-int.com

The articles and slides I've seen have all indicated Intel's first to manufacture with it rather than inventing it. Proof of concept is an extremely long way away from having something viable for manufacture. I believe an ARM based chip was the first to show backside power delivery and that was back in 2019 yet backside power delivery still isn't here. There's a lot to be said for successful implementation into a manufacturable product.

That is not to say I've seen everything and it's entirely possible some idiotic marketing has claimed such of course.

 

[bit_user]

Intel doesn’t offer a more detailed explanation as to why constructing an E-core with PowerVia technology improved the maximum frequency (fMax) of the core by 6%, though, I suspect it has to do with a higher voltage actually reaching the transistors themselves, allowing them to clock a bit higher.

I'd guess it has to do with the density increase. Higher density means shorter critical paths, which then lets you increase clock speed and still make timing. However, maybe it has more to do with power-efficiency.

Then again, @I_draw_on_bald_heads sounds like they probably know something about the subject, which puts them well ahead of me.

 

[Metal Messiah.]

It might be you guys are correct. Let me dive deep into more of the technical info behind this tech.