News Intel Flashes World’s First UCIe-Connected Chiplet-Based CPU

[Admin]

Intel CEO Pat Gelsinger displayed the first multi-chiplet package with the standardized UCIe interface at the company’s Innovation 2023 conference, marking the first public display of working UCIe-enabled silicon.

Intel Flashes World’s First UCIe-Connected Chiplet-Based CPU : Read more

 

[bit_user]

Intel’s chiplet-based processors, like Sapphire Rapids and the newly announced Meteor Lake, currently use a proprietary interface and protocol for communication between the chiplets, but Intel has announced that it will use the UCIe interface after its next-gen Arrow Lake consumer processors.

Actually, UCIe does allow for proprietary protocols. This was certainly necessary to gain widespread adoption by major players. That way, Nvidia can adopt it without foregoing NVLink and AMD needn't abandon Infinity Fabric - it's merely the physical and electrical aspects they'd benefit from. Even then, having standards should help with tooling, IP libraries, and ultimately time-to-market.

There's a good writeup of it, here:

Universal Chiplet Interconnect Express (UCIe) Announced: Setting Standards For The Chiplet Ecosystem

www.anandtech.com

"at the protocol layer, chiplet makers have a few different options. The official standardized protocols for UCIe are PCI-Express and its cache-coherent cousin, Compute Express Link, ...

... the promoters have made it clear that UCIe isn’t locked to just PCIe/CXL. Future versions of the standard may add other protocols if something comes along and the owner is willing to donate it to the standard.

Finally, chipmakers are also free to use their own custom/bespoke protocols as well; they are not restricted to using just PCIe/CXL. UCIe supports a raw/streaming protocol option that allows any other protocol to be used. Both chiplets would need to support this custom protocol to make a connection, of course, but even in this case, this would allow a chipmaker to leverage the physical aspects of the UCIe standard to simplify their own design/production."

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[PaulAlcorn]

Actually, UCIe does allow for proprietary protocols. This was certainly necessary to gain widespread adoption by major players. That way, Nvidia can adopt it without foregoing NVLink and AMD needn't abandon Infinity Fabric - it's merely the physical and electrical aspects they'd benefit from. Even then, having standards should help with tooling, IP libraries, and ultimately time-to-market.

There's a good writeup of it, here:

​

Universal Chiplet Interconnect Express (UCIe) Announced: Setting Standards For The Chiplet Ecosystem

www.anandtech.com

​

"at the protocol layer, chiplet makers have a few different options. The official standardized protocols for UCIe are PCI-Express and its cache-coherent cousin, Compute Express Link, ...​

​

... the promoters have made it clear that UCIe isn’t locked to just PCIe/CXL. Future versions of the standard may add other protocols if something comes along and the owner is willing to donate it to the standard.​

​

Finally, chipmakers are also free to use their own custom/bespoke protocols as well; they are not restricted to using just PCIe/CXL. UCIe supports a raw/streaming protocol option that allows any other protocol to be used. Both chiplets would need to support this custom protocol to make a connection, of course, but even in this case, this would allow a chipmaker to leverage the physical aspects of the UCIe standard to simplify their own design/production."​

​

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The article does not state that different protocols cannot be used. As I wrote in our initial coverage of the UXIe launch, "While the specification begins with PCIe and CXL as the current protocols, it will expand to include other protocols in the future." -- no need to quote AT at me.

 

[bit_user]

The article does not state that different protocols cannot be used. As I wrote in our initial coverage of the UXIe launch, "While the specification begins with PCIe and CXL as the current protocols, it will expand to include other protocols in the future."

The part I quoted from your article (at the top of my post) really made it sound like Arrow Lake will switch to using one of the official UCIe protocols. My point was that even in its current incarnation, UCIe does not mandate the use of PCIe or CXL for chiplet communication.

It's not only future versions of UCIe that potentially allow for other protocols. I took care to underline that part, so it'd be hard to miss.

The diagram was included to show that the protocol is only a part of what UCIe defines. Even if you give up the protocol layer, there's still a lot else. You might be aware of that, but others might not be attuned to it.

no need to quote AT at me.

It wasn't really directed at you, but rather anyone else in the comments. I don't presume authors read the comments (many/most don't) and I didn't even @-you, this time.

Again, thanks for your coverage. Try not to mind us nit-pickers, too much!
: )