There's a mismatch between the article and the info on ark.intel.com
The article states that the H610 chipset has 8 PCIe 3.0 lanes
According to ark.intel.com, it has 12 lanes:
https://ark.intel.com/content/www/us/en/ark/products/218829/intel-h610-chipset.html#tab-blade-1-0-4
Now that the entire line of Alder Lake processors has been released, I'm even more confused.
According to the specs from ark.intel.com:
Core i9/i9K: 8 P-Cores + 8 E-Cores / 30MB L3 / 14MB L2
Core i7/i7K: 8 P-Cores + 4 E-Cores / 25MB L3 / 12MB L2
Core i5K: 6 P-Cores + 4 E-Cores / 20MB L3 / 9.5MB L2
So far it's pretty consistent: (1.25MB L2 + 2.5MB L3) per P-Core, and (2MB L2 + 5MB L3) per 4xE-Cores
Core i5 (non K): 6 P-Cores +
0! E-Cores / 18MB L3 / 7.5MB L2 per P-Core
Core i3: 4 P-Cores + 0 E-Cores / 16MB L3 / 5MB L2 per P-Core
So no E-Cores at all, and 1.25MB L2 + 3MB L3 per P-Core (or just 'Core')
Looks like L2 is consistent across the board, but apparently Core i3 and Core i5 non-K have more L3 cache per core than the higher-end models?