News Intel May Bet on Stacked Forksheet Transistor Tech for Sub-2nm Chips

I am not super in on the marketing of "2nm" transistors, but the traditional definition is that they have 2nm of space between between themselves, right? I thought there was some sort of unresolved barrier at 2-4nm density due to some quantum physics related issues? Again, I am not the most informed as far as this goes. Is this actually a 2nm process in the traditional sense or is it marketing attached to a Xnm process?
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The nm metric is largely useless these days. It's morphed through history depending on who is showing off what. For many, many years Intel always measured from the outside edges of the contacts. Then it somehow became the smallest freestanding structure you can build. Then it turned into the thinnest line you can expose. Now it's just a name that has nothing to do with anything and is used as a marketing gimmick.
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