I don't really see any benefit of X86S other than slightly faster boot-times. My Linux system still boots in seconds.
The benefit is that it simplifies the CPU cores by getting rid of a lot of circuitry that's currently cluttering up key parts of it. Also, by simplifying the ISA spec, you reduce the number of test cases that new CPUs must be run through.
Trust me: Intel wouldn't go to this trouble just to streamline boot times by a negligible amount.
Actually, I think that Intel and AMD should instead bring back some segmentation features that were disabled in 64-bit mode.
Only FS and GS segments remain and they used to be bounds-checked and could be write-protected. The other segment register address prefixes are unused in 64-bit mode.
I can't really comment, as I never programmed x86 assembly in the 64-bit era. Is there even a use case for programs to have lots of segments? If it really made sense, then you might expect they'd be adding more segment registers in APX, but I don't recall reading anything about it.
BTW, access control is usually done via the page table. It scales much better than segments (or, at least it did in the 32-bit era).
This could help with running WebAssembly and in other compartmentalisation schemes, without needing kludges such as allocating 8GB chunks of address space and using MPK or whatnot.
Address space is cheap, though. 8 GB is only 33 bits out of 64. The underlying memory is what matters, and simply allocating address space doesn't equate to that.
What's MPK?
BTW. Itanium did actually have some SIMD instructions ... in general-purpose registers. They did not have the forethought to extend the register size over what MMX used to offer though.
I was repeating what someone who worked on it said. I guess they were referring to the way SSE added support for fp32 and fp64 data types, whereas MMX was only operating on integers.
BTW, I found an IA-64 instruction set manual, here. It does confirm MMX-like functionality, as you say: