• Happy holidays, folks! Thanks to each and every one of you for being part of the Tom's Hardware community!

News Intel outlines plan to break free from TSMC manufacturing — 70% of Panther Lake at Intel fabs, Nova Lake almost entirely in-house

Toggle sidebar Toggle sidebar
I thought they just started using them a couple of years ago, if that.
Intel really needs to figure out what the [] they are doing.
 
Last edited by a moderator:
mac_angel said:
I thought they just started using them a couple of years ago, if that.
Click to expand...
At first, it was just with Xe (Alchemist) dGPUs.

Then, about a year ago, Meteor Lake took it another step, with everything but the CPU tile and the base layer made on TSMC nodes (the IOE and SOC tile were made on N6, while the iGPU tile was made on N5).

Lunar Lake and Arrow Lake are now made entirely by TSMC, except for the base layer that interconnects everything.

So far, I think all of the tiles in Intel server CPUs are made by Intel.
 
  • Like
Reactions: atomicWAR
WTF are they being Wishy/Washy?

Go 100% "ALL-IN" on making every piece of silicon in-house.

There is ZERO Excuse to "NOT DO SO" when you have fabs sitting idle.

Figure out which tiles or chips need to be made, and what can be made with what you have.

That's the job of Intel's Design side having it's own "Fabs".

You're hurting your own company if you don't use your own capacity.

Look what happened with Meteor Lake & Lunar Lake.

You were slower, a train wreck, and still paided TSMC.

It's a Double Whammy. You failed to beat all your competitors, and you still left Fabs idle.

If you use your own fabs, even if you don't beat your competitors, you don't incur the "Idle Fab" penalty.

Then it's up to marketing to sell the rest of the existing volume to all your customers.
 
If the designs were good there would be no problem with earning enough margin to give both tsmc and Intel a nice profit. If intel would like to earn margins on their designs - have they considered making good designs? Because their current designs put them in fourth place in CPU efficiency...

I think it Kamen Rider Blade doesn't understand semiconductors. To have the most advanced process node factory you have to have dominance in many markets - more than just CPUs and 1% of GPUs. You need to dominate maybe CPUs GPUs cell phones and data center NPUs. The fabs cost $15B - $30B so you need to serve multiple markets to make money

Intel hasn't earned enough money to actually run the most advanced fabs in the world. For 20 years they have been haphazardly buying design companies outside of CPUs and then failing to grow those companies and then shutting them down.

So you can't just say ”Intel has the Fab they should use it!”. The Fab eats money like there is no tomorrow (like 5m+ per day shut down or $15m once you start production) and it takes hundreds of millions of investment to figure out how to build chips reliably after you've bought all the equipment and Intel lost $13.6 billion dollars last quarter which is one of the largest losses of any USA company in history!

Intel doesn't currently have a competitive working fab. They have the 18A fab but they haven't figured out how to make it work reliably yet. They made sample chips and gave them to Broadcom and Broadcom came back and said, "these are <Mod Edit> and we're going with TSMC" so they lost an early customer on 18A.

I would also like to point out that Pat gelsinger is a liar. He said they would do five process nodes in 4 years and the previous one 20a was skipped and now the final fifth one is 18a and it doesn't work and so he's done three process nodes in 4 years and will never achieve more than 4x. Pretty soon it will be 5 years for 3 nodes at end of Q2 2025 if 18a isn't in volume production by then ......
 
Last edited by a moderator:
  • Like
Reactions: rm12, P.Amini and atomicWAR
systemBuilder_49 said:
If the designs were good there would be no problem with earning enough margin to give both the tsmc and Intel a nice profit.
Click to expand...
This is an interesting point. AMD can clearly make competitive CPUs, while paying TSMC - why not Intel? Is it because Intel made its cores too big, under the assumption they'd be fabbed internally? Then, when Intel actually has to pay the market rate for silicon, we find out why AMD's cores have traditionally been smaller?
 
  • Like
Reactions: rm12, atomicWAR, TCA_ChinChin and 1 other person
bit_user said:
So far, I think all of the tiles in Intel server CPUs are made by Intel.
Click to expand...
The GNR IO tiles are Intel 7. I haven't seen anything specific said about SRF but it's a safe bet they're in house as well.
bit_user said:
This is an interesting point. AMD can clearly make competitive CPUs, while paying TSMC - why not Intel? Is it because Intel made its cores too big, under the assumption they'd be fabbed internally? Then, when Intel actually has to pay the market rate for silicon, we find out why AMD's cores have traditionally been smaller?
Click to expand...
I'm not sure we can really make any reliable conclusions when AMD's using a node that is significantly cheaper for the majority of their products.
 
thestryker said:
I'm not sure we can really make any reliable conclusions when AMD's using a node that is significantly cheaper for the majority of their products.
Click to expand...
If Zen 5 had more transistors than Intel and AMD were using a cheaper node, you might have a point.

As best I can tell, each Zen 5 core is 4.85 mm². The Lion Cove P-cores in Lunar Lake are estimated at 4.53 mm². I found a density estimate for N4P of 117.78 MTr/mm², but I didn't find one for N3B from the same place, and that important since the number bakes in a certain ratio of different cell types. So, I can't make comparable transistor count estimates, but I'm sure N3B is more than 7% denser than N4P.

Therefore, I stand by my claim that Zen 5 cores are cheaper than Lion Cove.
 
  • Like
Reactions: -Fran- and rm12
bit_user said:
Therefore, I stand by my claim that Zen 5 cores are cheaper than Lion Cove.
Click to expand...
I never said they weren't cheaper just that manufacturing cost absolutely affects margins. You cannot logically question Intel making low margins without also taking into account wafer costs.

As I'm sure you're aware the cost increase going from N5 to N3 is more than the density gains by a fair amount.
 
Admin said:
Intel is set to bring back in-house CPU production with Panther Lake and Nova Lake, but some products will still be made at TSMC.

Intel outlines plan to break free from TSMC manufacturing — 70% of Panther Lake at Intel fabs, Nova Lake almost entirely in-house : Read more
Click to expand...
I suspect Intel might be more profitable if they outsourced all fab work. Of course this doesn't help the US become less dependent on TSMC.

An alternative might be to sell off their fabs to another US company who could then pick up additional work from other sources. Fabless companies seem to be the ones doing best.
 
  • Like
Reactions: bit_user
tony-w said:
I suspect Intel might be more profitable if they outsourced all fab work. Of course this doesn't help the US become less dependent on TSMC.
Click to expand...
Yes. Fabs are expensive and capital-intensive. That's why Intel is trying to increase volume by fabbing chips for other people, in order to help fund their continued development. However, the project isn't very far along, yet.

tony-w said:
An alternative might be to sell off their fabs to another US company who could then pick up additional work from other sources.
Click to expand...
You mean like Global Foundries? That didn't work out, too well. They stopped trying to be a cutting-edge fab about 6-7 years ago. If IFS chases short-term profitability, rather than continuing to develop cutting-edge nodes, then the US will be entirely dependent on foreign-owned fabs, most of which are located outside of the USA.

tony-w said:
Fabless companies seem to be the ones doing best.
Click to expand...
Yes, this is news to no one. Fabless semiconductor companies have cost structures much closer to that of software companies.

IMO, Intel must eventually spin off their fabs, but the key question is: "when?" Doing it now wouldn't be in anyone's long-term best interests (except TSMC and Samsung's).
 
  • Like
Reactions: -Fran-
PG said in the earnings call ... the AZ 18a fabs aren't going into production until 2H 2025, and that their 18a yields aren't currently ready for HVM.

So they don't really have a choice to bring everything back in-house. Besides, they can still expand their market share by building tiles at TSM.

Intel currently has an advantage in advanced packaging capacity, and they're using it for their consumer chips.
 
  • Like
Reactions: bit_user and phead128
Intel's 300mm optical fab process will become important over the next few years as pcie/cxl over optical becomes a thing. Remote cxl memory pools becomes a thing. The latency issue can go away by using push.

So, does Thunderbolt go optical? I think so. AI laptop PCs are just going to be laptops with a Thunderbolt optical interface. You'll have to have some external AI processor unit with a bunch of memory.
 
why cancel 20A in-house to focus on 18A in-house, only to do 18A partially in-house? I swear they are hedging in case 18A does not yield well, and to try to get partial CHIPS ACT payout with some in-house manufacturing, but the fact it's not 100% just tells you 20A cancellation was not about overconfidence in 18A.
 
  • Like
Reactions: TCA_ChinChin, rm12 and bit_user
bit_user said:
If Zen 5 had more transistors than Intel and AMD were using a cheaper node, you might have a point.

As best I can tell, each Zen 5 core is 4.85 mm². The Lion Cove P-cores in Lunar Lake are estimated at 4.53 mm². I found a density estimate for N4P of 117.78 MTr/mm², but I didn't find one for N3B from the same place, and that important since the number bakes in a certain ratio of different cell types. So, I can't make comparable transistor count estimates, but I'm sure N3B is more than 7% denser than N4P.

Therefore, I stand by my claim that Zen 5 cores are cheaper than Lion Cove.
Click to expand...
I think the density metric for a fab process is becoming a difficult one to use as the chip design (mix of structures) seems to have a large effect on the MTr/mm2 of the final product.
 
  • Like
Reactions: -Fran-
JayNor said:
Remote cxl memory pools becomes a thing. The latency issue can go away by using push.
Click to expand...
I'm a big believer in CXL, but latency never completely goes away. I think the latency of CXL does tend to get overstated, as it potentially scales better than conventional memory systems and so I think typical latency might not actually be that different. Not to mention that prefetching can mitigate latency, as can having a fast memory tier (e.g. HBM) on package.
 
  • Like
Reactions: -Fran- and phead128
jp7189 said:
I think the density metric for a fab process is becoming a difficult one to use as the chip design (mix of structures) seems to have a large effect on the MTr/mm2 of the final product.
Click to expand...
Yes, but my assumption is that these CPU cores have a roughly similar mix. So, if we use some composite density figures for two nodes that presume the same mix of structures, the errors will be somewhat proportional and therefore mostly cancel out, when doing comparisons.

Anyway, I've found a figure of N4P having a 6% composite density increase vs. N5[1]. According to the second link, N3B scales SRAM 5% more densely than N5, but logic is 60% more dense. I'm not going to speculate on what the comparable shrink would be, for these CPU cores, but with logic dominating the core itself, I'm sure the scaling is well better than the 7% threshold that would need to be met for Lion Cove to have more transistors than Zen 5.

Sources:
  1. https://fuse.wikichip.org/news/6439...ily-with-a-new-enhanced-performance-n4p-node/
  2. https://fuse.wikichip.org/news/7375/tsmc-n3-and-challenges-ahead/
 
  • Like
Reactions: -Fran- and jp7189
  • Like
Reactions: jp7189
Admin said:
Intel is set to bring back in-house CPU production with Panther Lake and Nova Lake, but some products will still be made at TSMC.

Intel outlines plan to break free from TSMC manufacturing — 70% of Panther Lake at Intel fabs, Nova Lake almost entirely in-house : Read more
Click to expand...
Production has not been the problem at Intel but rather their inept managers that are too distant from the market. They failed to consider Nvidia as either a threat or an opportunity, much as they have done with AMD. Intel decided to embed graphics processing inside the CPU which is good for compact office computers and laptops but ignored the entire gaming and graphics and video editing markets.
 
You must log in or register to reply here.

TRENDING THREADS

Latest posts

Moderators online

Share this page

COMPANY
RESOURCES
FOLLOW
Top Bottom