News Intel Panther Lake samples with flagship 18A node have been powered on at eight customers — Co-CEOs dispel rumors regarding poor silicon health

Better than nothing.
Still a possibility it will win, and 18a will at least equal anything from TSM.
But, ongoing yield and cost issues will continue to haunt everyone.
 
PTL/CWF are both very important from a product and foundry standpoint. PTL should bring Intel's margins back in line with where they expect to be while also being a client showcase for 18A. CWF while not as important on the margin side (all Xeons are built on Intel nodes) it will be extremely important for the enterprise market in scale and performance. From a foundry perspective I don't think this will end up being much different size wise than PTL since all available information indicates 24 core tiles.
What's the usual time between OEMs getting engineering samples and laptops reaching the market? Like 6-9 months or something?
That sounds about right, but in this case I'd assume we're talking mid-late fall releases at the earliest since ARL laptops won't launch until next year. While I'm sure the OEMs and Intel would both like to have best foot forward they also want to be able to sell existing stock.

I do think that the ARL laptop chips will probably be the least produced of recent history due to PTL seemingly being on track and the cost of TSMC N3 manufacturing.
 
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What's the usual time between OEMs getting engineering samples and laptops reaching the market? Like 6-9 months or something?
Panther Lake is due for release in H2 2025, but probably late Q3 if things go to plan. Also, let's not forget their server cpu Clearwater Forest is also built on 18A and due next year.
 
A lot of the disinformation I am sure coming out of foreign competitors, who'd love it if the U.S. failed hard at our fabs.
Disinformation? You mean reality?
Intel 20A was supposed to be the first customer node and they dropped it. Doesn't instill confidence that we know that all intel really can do is for themselves... And why ARL went to N3?
 
Disinformation? You mean reality?
There's zero evidence supporting the claims against 18A being "reality". Most of the reporting has been dishonest at best. While I don't think there's some grand conspiracy it's very likely that at least some of it is being done by investors trying to maximize short term profits.
Intel 20A was supposed to be the first customer node and they dropped it.
This was supposed to be a one and done node which means their reasoning for dropping it is believable, especially after Intel 4. However until 18A appears nobody will know whether or not this was the real reason. That's the only reality of the situation: Intel has stated their reason, but that's the only actual information available.
And why ARL went to N3?
It was supposed to be on 20A, but the node was canceled and LNL was already on N3. In theory this makes doing ARL on N3 faster than making it work on Intel 3 and frees up EUV capacity in the process. Assuming 18A is actually hitting its timelines this is the most logical approach for the long term health of IFS.
 
What's the usual time between OEMs getting engineering samples and laptops reaching the market? Like 6-9 months or something?
6-9 months for a new part of this complexity on a new process seems like an aggressive schedule. If everything goes right it is reasonable, but I would expect evaluation phases and 2 or 3 loops through the fab to fix bugs and make changes to optimize process yields. This puts it at 9 to 15 months. First parts came off of the fab over a month ago.
 
A lot of the disinformation I am sure coming out of foreign competitors, who'd love it if the U.S. failed hard at our fabs.
Engineering samples powering on doesn't imply anything about yield at HVM scale though.

Pat Gelsinger famously handed an 18A engineering sample to Lenovo CEO, then he got fired. So what does that say about 18A health with just passing out initial samples to customers?

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Pat shows engineering sample of 18A to Lenovo just four weeks before he got fired.

TLDR: engineering samples does not imply healthy HVM yields at scale.