Intel says Penryn "complete"

shinigamiX

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http://www.engadget.com/2007/01/17/intel-sez-penryns-done-lookout-for-45nm-wolfdale-yorkfield/

SSE4? Sounds spiffy. I'm a bit confused, however, as to what Wolfdale is supposed to be. A Conroe replacement? Then what is Penryn?

EDIT: I can't read. Or spell.
 

MU_Engineer

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The dual-core Penryn laptop chip would probably be the best chip for Intel to make 45nm first as it's the one that could benefit most from power/heat reduction. Next would be taking care of the Kentsfield's horrible thermal properties- that looks to be Yorkfield. I guess since Intel's not making a monolithic quad-core right off of the bat with the 45nm process, that will also mean a lot of 45nm Core 2 Duos will be shot too.

Two questions, Jack: Intel supposedly is introducing both MCM (Yorkfield) and monolithic-die quad-core CPUs (Wolfdale) on the 45nm process using the same micro-architecture while an 8-core CPU is not on the roadmap. If the FSB isn't a problem for shuffling data between the two core banks, why go through the expense of making a new die mask and getting the slightly lower yields of chips? Or do you think there will be enhancements like a shared L3 cache for all the cores that requires a monolithic die like the K8L?

The other thing I was wondering about was that a monolithic quad-core die gives Intel the capability to make an 8-core MCM. This could happen as soon as Intel ships the Wolfdale, which from what I heard will be about a year from now. There is no 8-core chip on the roadmap, so when/if do you think Intel might do that? It seems like a logical step except for having to feed the cores with enough memory bandwidth. I've heard that DDR2 or DDR3-1333 memory should be out about a year from now. Making a dual-channel setup with 1333 MHz RAM should be enough bandwidth to feed 8 cores (apparently dual channel 1066 is enough to feed 4 in the Kentsfield.) But thinking about getting the bandwidth to the cores brings up a few issues:

1. I don't think that an FSB of over 2000 effective MHz is possible unless chipsets improve drastically. Even if we say that doubling Kentsfield's FSB from 1066 to 2133 is all that's needed, 2133 is about as high or higher than even the most skilled overclockers hit with current chipsets, forget 2666 MHz to deliver the bandwidth from dual-channel 1333 MHz RAM. So would reworking the FSB to pump in more data per access (perhaps 128 bits instead of 64 bits) or running dual 1333 MHz FSBs to one socket work?

2. An integrated DRAM controller would be able to handle the RAM just fine- AMD's AM2 X2s have a RAM bandwidth equivalent to a 1600 MHz FSB and I heard rumors that the K8L will address DDR2-1066. But I don't think this is possible for Intel to do without a monolithic core, and that would mean 32nm.

So is that why we don't see an 8-core CPU on Intel's roadmaps?
 

MU_Engineer

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That is true. But processors often work on very large data sets- sometimes gigabytes in size. And also, what gets into the cache from RAM must at some time be returned from cache to RAM after it's gotten worked on. So unless the cache is a significant portion of the system memory. I suppose that with optimal prefetching methods, perfect cache hits, and less than peak CPU usage on all cores that the FSB doesn't have to be as wide as the aggregate data demands of all of the CPU cores as the pertinent data will be stored in cache, shuffled in and out at the FSB's leisure. But I can't see how one can double the core count without significantly increasing the bus bandwidth and/or cache size. Adding extremely large caches gets to be really expensive after a while and kill yields, so I think that the sizes won't balloon that big.

I suppose there could be an external FSB to the chipset and an internal, non-FSB communication system like the ring bus on ATi's GPUs to carry inter-MCM data like snoops. That would relieve the FSB of the burden of carrying that data too. But I'd still think the FSB would need to get significantly stouter than it is today.
 

MU_Engineer

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I'd at least think that it would show up for servers. More cores in fewer sockets is much more economical than fewer cores in more sockets and can lead to even higher core densities in servers. It would be really popular in HPC applications and for rendering/encoding, but yeah, that's 1% of the population or less. But I guess Intel also has a vested interest in keeping the MP segment alive as the margins on the CPUs, chipsets and boards are far more than they'd get on a 2P board with a 2P chipset and a DP CPU. Or keeping the DP segment from getting cannibalized by single-socket, multi-core CPUs and consumer-priced RAM, boards, and chipsets.
 

ritesh_laud

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If the FSB isn't a problem for shuffling data between the two core banks, why go through the expense of making a new die mask and getting the slightly lower yields of chips? Or do you think there will be enhancements like a shared L3 cache for all the cores that requires a monolithic die like the K8L?
While waiting for Jack's answer, I'll take a stab: Shared L3 is probably part of it, but I'd guess that improved power management ala K8L is the main driver. A monolothic die allows incorporating central power management logic that enables on-the-fly switching on/off of cores as needed, or running cores at different speeds. Also, with the planned integrated memory controller in Nehalem Intel will eventually have to go monolothic anyway.
 

MU_Engineer

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While waiting for Jack's answer, I'll take a stab: Shared L3 is probably part of it, but I'd guess that improved power management ala K8L is the main driver. A monolothic die allows incorporating central power management logic that enables on-the-fly switching on/off of cores as needed, or running cores at different speeds. Also, with the planned integrated memory controller in Nehalem Intel will eventually have to go monolothic anyway.
Power management...that's an excellent reason and one I didn't think of off the top of my head. I know Intel will make an IMC-equipped chip and that will need an IMC, but I thought that wasn't supposed to come until Nehalem. I think Nehalem will be 45nm, so perhaps making a MCM -> monolithic die and integrating the improved power management before that change in architecture would help them get any bugs out.
 

pausert20

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Since Intel plans to launch the Nehalem processor in 2008 and it is a complete core redesign I'm expecting that they will need to get samples out from the factory in Q3 of this year if they want to launch a product before the end of Q4.

Wolfdale is a dual core part and I have not heard of any monolithic processor coming out from Intel until 2008. This means that Yorkfield with be a faster and hopefully cooler running version of Kentsfield.

Be nice to have a Yorkfield with 6 + 6 Megs of Cache and running at 3.67GHz still within the 130w DTP thermal envelope. At least that is what I'm hoping for.
 

pausert20

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The rumor I heard is that the Cache on the high end Nehalem processors will again increase. But with a IMC I'm not sure how important that becomes but it will sure speed up the system if the main memory will need to be access if there is a cache miss in the L2 section.
 

MU_Engineer

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JumpingJack said:
The MCM approach has two distinct advantages and one distinct disadvantage. The disadvantage is already out --- the snoop and coherency across the FSB. The two advantages are of course well known too and you mentioned it -- time to market and yield. I don't think Intel will move to a monolithic core before the end of 2007 on the current architecture, but that remains to be seen. One thing though that there is not clear answer --- will the FSB bottleneck a quad core Penryn derivative. We don't know --- the FBS will jump to 1333 MHz, giving a full 10.5 GB/sec BW to the socket, but the clock speed of the processor will also scale up, reportedly to 3.5-3.7 GHz. 333 is 33% icnrease but so is the rumored release speed (slightly over 33%). So scaling wise, there should be no difference in observed bottlenecks than what we observe for stock Kentsfield on a quad --- which is none.
I didn't think that there would be any problems with the current FSB setup and quad-core chips- the effective 1066 MHz on the Kentsfiels *seems* to be enough. And like you said, the 1333 MHz FSB has already been done and that should allow an extra 33% in clock speed. I was wondering about a possible 8-core CPU, but that does not seem to be in the works. Perhaps I'll revisit that one when people are talking about 8-core x86 CPUs in a year or two.
All in all it will be a wait and see game.... I am working now to find the FSB limitations on the current quad, and once I find that point I can give you a more reasonable estimate. But to answer your questions, the monolithic quad core design is not on the horizon at least not from any clear cut roadmap and 2nd, the next major revision with the IMC/CSI will do away with any debate about FSB issues.
It will be interesting to see how the FSB on the Kentsfield affects performance. Do your testing on the QX6700 and get back to us, we'd like to see the results.
What I wonder is if Intel will keep the large L2 cache with an IMC --- my guess is no, or if they do, there will be a larger gradation of different cache sizes to choose from...
I bet you'll be right too. AMD did just that with their K8s and the integrated memory controller with its lower latencies and higher bandwidth to RAM made large caches less useful. The caches sizes used by Intel are mostly there to mediate the FSB's delay in data I/O. Also with the monolithic core chips, large caches make for large individual dies that drive prices up and yields down.

The current 65 nm 4MB L2 Core 2 Duo Conroe dies are 144 mm^2 and the 65 nm 2MB Core 2 Duo Allendale dies are 111 mm^2. That would put a 6MB L2 cache Core 2 Duo on 65 nm at 177 mm^2, and a shrink of that to 45 nm would make an 88.5 mm^2 die, which is what Wolfdale is supposed to be. A monolithic 45 nm quad-core with the purported 12MB L2 could thus be no smaller than 177 mm^2, and probably a bit bigger as the IMC and such would add extra transistors and surface area. If we call the area 190 mm^2. That's not a huge chip, but it's not small, either. If Intel puts roughly as much cache on the die as AMD will for the K8L, that will be about 6MB total, which would halve the die area required for cache and drive the die size down to about 140 mm^2. That's the size of the current Core 2 Duo and seems to be a size that is conducive to good yields and low costs.

EDIT: If you are looking for what might be exciting or novel from Intel this year....

- Watch 45 nm, the rumor mill is amiss with high-k, if this is true AMD will not hold the performance crown in 2007 and we will need to look to 2008 for what migh be competitive against Nehalem. But with an IMC and the BW that goes with that, well, AMD has their work cut out for them.... it will be interesting.
AMD has a reputation for being very quiet with things until they actually happen. The ATi acquisition, 65 nm processors, QuadFX...we weren't told that they really did exist until they happened for the most part. From the floor plan on the K8L, it looks to be a very competitive design and we'll see how well it does later this year.

- I would not be surprised if Intel cuts in a dual FSB on the high end Bearlake chipset and produces a dual socket workstation/DT MB in the same vain as AMD's 4x4 -- just to keep up with the core race as AMD will tout 8 cores on the board when barcelona hits. This is purely speculation... however, they already know how to do it as broadwater already employees a 64 meg Snoop filter chipset with dual FSBs, I could see a DT variety with say a 32 Meg or 16 Meg snoop filter and dual FSBs.
I'd not be surprised if Intel does this IFF AMD sells a lot of QuadFX units. If the QuadFX doesn't do all that well, Intel won't bother as the people who'd want 8 cores on one board could just buy Xeon DPs as they'd functionally be the same, except that a desktop variant would likely be significantly less expensive and use normal DDR2 instead of FB-DIMMs.

I think that the dual-socket units with normal DDR2 memory would do well if sold as top-level workstations instead of gaming machines. They would be more expensive than normal UP desktops but not nearly as big of a jump to a current server-based DP system with buffered ECC RAM and such that's probably not needed on what's basically just a very powerful desktop. If the concept is still around in a few years, and I hope it is, I'd buy one of these type of platforms as the cost to entry to a lot of cores is much reduced over buying server parts.
 

balister

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The thing that has really got me wondering is how much longer Intel plans to continue with the LGA775 socket. It's now been almost 3 years since this socket was introduced and I have to wonder if there may be a new socket coming in this year or early next. It would be nice if Intel would put out some kind of literature, either a white paper or a road map, showing when a new socket may be coming.
 

Barcelona_Xtreme

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How silly are AMD going to look if Intel launches 45 nm before K8L? :lol:
You will be the silly one becasue a 45nm die shrink won't put a threat to AMD's Barcelona.

Penryn will just be a die shrink of the C2D architechture and some added SSE4 instructions.

You have to remember that AMD will refine 65nm even more and we still don't know Barcelona/K8L (or call it how you want it) final specs.

Also, AMD will debut 45nm with Ultra-Low-K and DC 2.0 in the 2008 timeframe. Definately, intel is not in the lead or the king of the hill like how many tend to believe and not everything is doom and gloom for AMD.
 

atp777

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How is Intel not in the lead? I see better products with competetive pricing.

If Core 2 is better, then I would say, yes, they are in the lead. As Jack has said many times, It's about the data and I've seen the Benchmarks. :)
 

grifter33

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The thing that has really got me wondering is how much longer Intel plans to continue with the LGA775 socket. It's now been almost 3 years since this socket was introduced and I have to wonder if there may be a new socket coming in this year or early next. It would be nice if Intel would put out some kind of literature, either a white paper or a road map, showing when a new socket may be coming.
Socket B and Socket H are supposed to come out with the Nehelem chips in 2008. I don't think much more than that is known at this point.

LINK
 

cb62fcni

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How silly are AMD going to look if Intel launches 45 nm before K8L? :lol:
You will be the silly one becasue a 45nm die shrink won't put a threat to AMD's Barcelona.

Penryn will just be a die shrink of the C2D architechture and some added SSE4 instructions.

You have to remember that AMD will refine 65nm even more and we still don't know Barcelona/K8L (or call it how you want it) final specs.

Also, AMD will debut 45nm with Ultra-Low-K and DC 2.0 in the 2008 timeframe. Definately, intel is not in the lead or the king of the hill like how many tend to believe and not everything is doom and gloom for AMD.

Nope, you're right. Intel is way behind. I wonder if they'll ever catch up.
 

salvador

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How silly are AMD going to look if Intel launches 45 nm before K8L? :lol:
You will be the silly one becasue a 45nm die shrink won't put a threat to AMD's Barcelona.

Penryn will just be a die shrink of the C2D architechture and some added SSE4 instructions.

You have to remember that AMD will refine 65nm even more and we still don't know Barcelona/K8L (or call it how you want it) final specs.

Also, AMD will debut 45nm with Ultra-Low-K and DC 2.0 in the 2008 timeframe. Definately, intel is not in the lead or the king of the hill like how many tend to believe and not everything is doom and gloom for AMD.

Still seeing pigs flying around, eh, barcelona? You do know what usually comes with a die shrink yeah? Higher clocks but remaining on the same power-level? Yes, thats right.

Lets say, theoretically, if Barcelona/K8L debuts with a 2 - 2,8 Ghz range, and Intel manages to release up to 3,5 Ghz (still remaining on same power-level as Conroe). Hands down, who do you think will win? Hey, who am I kidding. We'll just have to wait and see.

Hope they showcase a Yorkfield on IDF. :twisted: Clocking down.
 

dasickninja

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How silly are AMD going to look if Intel launches 45 nm before K8L? :lol:
You will be the silly one becasue a 45nm die shrink won't put a threat to AMD's Barcelona.

Penryn will just be a die shrink of the C2D architechture and some added SSE4 instructions.

You have to remember that AMD will refine 65nm even more and we still don't know Barcelona/K8L (or call it how you want it) final specs.

Also, AMD will debut 45nm with Ultra-Low-K and DC 2.0 in the 2008 timeframe. Definately, intel is not in the lead or the king of the hill like how many tend to believe and not everything is doom and gloom for AMD.
Are you bloody serious?
 

1Tanker

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How silly are AMD going to look if Intel launches 45 nm before K8L? :lol:
You will be the silly one becasue a 45nm die shrink won't put a threat to AMD's Barcelona.

Penryn will just be a die shrink of the C2D architechture and some added SSE4 instructions.

You have to remember that AMD will refine 65nm even more and we still don't know Barcelona/K8L (or call it how you want it) final specs.

Also, AMD will debut 45nm with Ultra-Low-K and DC 2.0 in the 2008 timeframe. Definately, intel is not in the lead or the king of the hill like how many tend to believe and not everything is doom and gloom for AMD.
Are you bloody serious?His name should be...Rose_Colored_Glasses_Xtreme. :roll:
 

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