News Intel Stratix 10 DX Introduces PCIe 4.0, Cache-Coherency via UPI

May 31, 2019
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nice article.
I believe the intel/mobileye eyeq5 chip also has pcie4 interface. Perhaps it was their first sampled chip with that.

It isn't clear to me how this UPI is different from UPI already used for the multi-socket server boards. Also, one of the other articles I read said the UPI is available now.

The ice lake server chip is already sampling, and includes pcie4.
 
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bit_user

Splendid
Herald
PCIe Gen4 support raises the question how this will be leveraged because Intel does not have any CPUs yet that support it
I'll bet AMD and IBM will sell a few more CPUs to host these, in the meantime. As long as you don't need Optane memory and just want to use the PCIe card form factor (i.e. no UPI), Epyc is now the go-to for PCIe.

the ARM subsystem and HBM2 memory aren’t available simultaneously in any of the three configurations
So, it's a tile? Or just conflicts in other ways? I was thinking it must annoy Intel to see those ARM cores in there, but their customers probably wouldn't have it if Intel tried to swap them for, say, Tremont cores. However, if they're demoted to a tile, that would let Intel start edging them out.
 

bit_user

Splendid
Herald
I believe the intel/mobileye eyeq5 chip also has pcie4 interface. Perhaps it was their first sampled chip with that.
Well, that is an embedded SoC, and they note that PCIe can be used to link multiple EyeQ5's. So, it lacks the incongruity of a PCIe 4-enabled server add-in.
EyeQ®5 implements two PCIe Gen4 ports for inter-processor communication, which could enable system expansion with multiple EyeQ®5 devices or for connectivity with an application processor.
Also, the EyeQ5 is slated to for a 2020 launch, according to that.

It isn't clear to me how this UPI is different from UPI already used for the multi-socket server boards.
But that's the point - it is the same. The point is that you could put one (or more) of these FPGAs on a server board and link it to the CPU(s) via UPI. Furthermore, that's the only way to make it cache-coherent, in this generation.
 

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