News Intel to Show Off E-Core-Based CPU with Backside Power Delivery

[Admin]

Intel to describe benefits of PowerVia backside PDN with 4nm-class test chip.

Intel to Show Off E-Core-Based CPU with Backside Power Delivery : Read more

 

[kal326]

It kind of looks like the top of a Pentium MMX got the die of a Coppermine chip.

 

[Friesiansam]

Intel to describe benefits of PowerVia backside PDN with 4nm-class test chip.

Intel to Show Off E-Core-Based CPU with Backside Power Delivery : Read more

"Backside Power Delivery", AKA Arse Power?

 

[cyrusfox]

Arm is interested, If TSMC does not have comparative tech, Could see Intel regaining Apple as a customer, albeit as IFS in the future.

 

[Co BIY]

This general reader needs more background.

Where is the power routed in current chips?
Is this basically a chip stacking tech - with a power layer being the base ?
What is cell utilization ?

 

[JamesJones44]

Arm is interested, If TSMC does not have comparative tech, Could see Intel regaining Apple as a customer, albeit as IFS in the future.

Definitely IFS. I think Intel would have to blow away the competition for a fair amount of time with their own designs if Apple were to give up on their own chips at this point.

 

[TerryLaze]

Definitely IFS. I think Intel would have to blow away the competition for a fair amount of time with their own designs if Apple were to give up on their own chips at this point.

It would be about the manufacturing process not the design, ifs is made to be able to handle different designs.
That's how they work with ARM now to make new ARM CPUs in the first place.
If ifs could handle apples designs and make them better by having better tech then apple could end up using them.
It's a big giant if and I don't think it will happen either but if then it could happen as fast as intel could adapt their fabs to the new designs.

 

[Kamen Rider Blade]

I think IFS would be better off if they split up from Intel's design side and become a Pay for Play Foundary, just like TSMC & GlobalFoundaries

 

[usertests]

A chip that will never be mass produced will show the benefits of a crucial technology.

If they're messing around with Crestmont E-cores, then maybe we'll see a Meteor Lake-N sooner than... 2025?

Give it 2 memory channels this time.

 

[Co BIY]

Arm is interested, If TSMC does not have comparative tech, Could see Intel regaining Apple as a customer, albeit as IFS in the future.

Sounds like TSMC also has plans for a backdoor...

TSMC Outlines 2nm Plans: N2P Brings Backside Power Delivery in 2026, N2X Added To Roadmap

 

[Co BIY]

This article answered some of my questions..

Backside Power Delivery and Bold Bets at Intel

 

[bit_user]

If they're messing around with Crestmont E-cores, then maybe we'll see a Meteor Lake-N sooner than... 2025?

Except that this is Backside Power Delivery being tested on Intel 4. That makes it a nonstandard Intel 4, which is why this is a test chip and not real product.

Intel isn't officially supporting backside power delivery (AKA Power Vias) until Intel 20A.

Give it 2 memory channels this time.

Yes, but it would need more cores to justify that. I think only the 8-core Alder Lake-N can really justify dual-channel DDR5. Plus, the sad reality is that Intel probably saw that 90% of their E-CPUs were being implemented with only one channel and felt it was a waste even to build-in the second channel.

Sounds like TSMC also has plans for a backdoor to take it up the backside...
🤣

TSMC Outlines 2nm Plans: N2P Brings Backside Power Delivery in 2026, N2X Added To Roadmap

Yes, I was going to post that same link. The key difference being that TSMC will lag in this respect, for a whole ~2 years.

 

[bit_user]

Where is the power routed in current chips?

The short answer is that power and data are currently both routed in from the same side of the chip.

Is this basically a chip stacking tech - with a power layer being the base ?

This is independent of chip-stacking. I'm not sure how much relevance it has for chip stacking (i.e. if it makes it easier, etc.), or if it's completely independent.

What is cell utilization ?

Referring to the % of die area that can be used for logic cells, I think. Ideally, you want 100% of die area to be consumed by cells, but routing & other constraints result in actual densities that are less. By getting power delivery "out of the way", it enables denser logic.

The benefit of higher density is basically to improve the cost-efficiency of the chips. Also, packing more logic in a smaller area means data has to travel shorter distances, which can translate either into higher clockspeeds or a greater amount of work being done per clock cycle.

Don't get too excited, because thermal density is becoming an increasingly limiting factor. High density is therefore most beneficial to low-power chips, like phone SoCs.

 

[Kamen Rider Blade]

Sounds like TSMC also has plans for a backdoor...

TSMC Outlines 2nm Plans: N2P Brings Backside Power Delivery in 2026, N2X Added To Roadmap

You might want to re-phrase that statement.

You mean BackSide Power Delivery.

 

[Kamen Rider Blade]

Referring to the % of die area that can be used for logic cells, I think. Ideally, you want 100% of die area to be consumed by cells, but routing & other constraints result in actual densities that are less. By getting power delivery "out of the way", it enables denser logic.

The benefit of higher density is basically to improve the cost-efficiency of the chips. Also, packing more logic in a smaller area means data has to travel shorter distances, which can translate either into higher clockspeeds or a greater amount of work being done per clock cycle.

Don't get too excited, because thermal density is becoming an increasingly limiting factor. High density is therefore most beneficial to low-power chips, like phone SoCs.

The 100% die are utilization is "Theoretical". realistically, you still have to have some power lines going to some points on the logic area. it can't be 100%, just close.

Also, why do I get the feeling that the BPN (Backside Power Node) needs a Heat Sink of some sort and cooling.

Given it's location on the Flat Contacts, I would expect it to be very difficult to cool unless something is designed for cooling that area.

 

[TerryLaze]

Don't get too excited, because thermal density is becoming an increasingly limiting factor. High density is therefore most beneficial to low-power chips, like phone SoCs.

Intel keeps all the things together keeping the surface area big and easy to cool so that you can cool a 13900k with a $20 cooler without losing performance, and the mock ups of meteorlake also shows them keeping everything together despite it being based on tiles so hopes ARE high, they don't split things up into multiple very dense hot spots making the CPU terrible to cool.

For far far in the future intel is already investing in alternate cooling like peltier/cryo or we had this news just a short while ago.

Intel Dives into the Future of Cooling

Intel research and collaborations in thermal technologies help extend Moore’s Law and improve sustainability of data centers.

www.intel.com

 

[bit_user]

you can cool a 13900k with a $20 cooler

Again, that's irrelevant because this is an article about Intel 4. And not even standard Intel 4, but a modified variant intended to evaluate their PowerVias. Please don't thread-jack to work your agenda.

 

[TerryLaze]

Again, that's irrelevant because this is an article about Intel 4. And not even standard Intel 4, but a modified variant intended to evaluate their PowerVias. Please don't thread-jack to work your agenda.

It's not irrelevant because they will have the same basic topography with everything being one big large area to cool, so the capability to cool current gen is very much relevant.

 

[bit_user]

It's not irrelevant because they will have the same basic topography with everything being one big large area to cool,

Specifically what topography are you talking about? The high-level floorplan of Meteor Lake sure isn't the same, with the CPU cores scrunched into one corner.

 

[TerryLaze]

Specifically what topography are you talking about? The high-level floorplan of Meteor Lake sure isn't the same, with the CPU cores scrunched into one corner.

It's all packed together creating one large surface area making heat dissipation easier just as it is on the current CPUs.

 

[bit_user]

It's all packed together creating one large surface area making heat dissipation easier just as it is on the current CPUs.

Huh? How is "packing together" supposed to be a good thing? When you have multiple hot things, you'd like to space them apart, so the heat from one can be dissipated without interference from others.

I think you're reaching... Please, let's just try to stay on topic.