News Intel's CEO says Moore's Law is slowing to a three-year cadence, but it's not dead yet

[Admin]

Intel's CEO Pat Gelsinger says transistors now double every three years instead of two, which isn't exactly Moore's Law.

Intel's CEO says Moore's Law is slowing to a three-year cadence, but it's not dead yet : Read more

 

[Bluetooth!]

I agree with him that chiplets keep Moores Law going forward and don't think we have to call it a new version (if the thought is focusing on the compute).

 

[vern72]

Eventually, you can't beat physics. Electrons can't change their size.

 

[JeffreyP55]

Eventually, you can't beat physics. Electrons can't change their size.

No such thing as future proof but the AM4 socket boards are still selling almost eight years later. Upgrade the CPU, flash the BIOS + maybe a couple of other things, you're good to go. Unless of course if you have the upgrade bug and or more money than sense. Eight or 9 years is a good run without a doubt. Moore's law is now showing its flaws and age.

 

[bit_user]

Gelsinger said that despite this apparent slowing of Moore's Law, Intel could create a 1-trillion transistor chip by 2030,

Ah, but at what price? It's no use, if it's not economically viable. If you think GPU prices are bad today...

"For all of the critics that declare we're dead... until the periodic table is exhausted, we ain't finished."

Obviously, not all elements are equally plentiful.

However, perhaps quantum computers could discover new materials that keep the game going just a bit longer.

Still, Gelsinger admitted that Moore's Law's economic side is breaking down. "A modern fab seven or eight years ago would have cost about $10 billion. Now, it costs about $20 billion, so you've seen a different shift in the economics."

Yup. It's like this:

​

Sorry that it's old and I don't know the true origin. If anyone has more up-to-date data, please share.

 

[TerryLaze]

Eventually, you can't beat physics. Electrons can't change their size.

You don't have to use electrons though, they do now because it's the cheapest way to do it but they could use photons in the future (optical computing) , or a range of other things.

 

[TerryLaze]

Ah, but at what price? It's no use, if it's not economically viable. If you think GPU prices are bad today...

If you are the only company with a product that people want then it will be economically viable even at a very high price.
Also the server/professional market will pay for it, as always, and it will trickle down to consumer stuff later.

 

[kjfatl]

Ah, but at what price? It's no use, if it's not economically viable. If you think GPU prices are bad today...


Obviously, not all elements are equally plentiful.

However, perhaps quantum computers could discover new materials that keep the game going just a bit longer.


Yup. It's like this:

​

​

Sorry that it's old and I don't know the true origin. If anyone has more up-to-date data, please share.

The chart, relative to 28nm is likely do drop for a number of reasons.
- Competition: With TSMC as the only supplier of smaller geometries, they have no incentive to lower price. With Intel now in the market, TSMC alone no longer sets the price.
- Equipment amortization: Processes than used to have 2 or 3 year effective life are moving to 20 to 30 year life. Once much of the equipment is in place and paid for, the operation and maintenance costs start to dominate. This goes across the supply chain to materials and mask generation as well.
- Node optimization.

 

[bit_user]

The chart, relative to 28nm is likely do drop for a number of reasons.
- Competition: With TSMC as the only supplier of smaller geometries, they have no incentive to lower price. With Intel now in the market, TSMC alone no longer sets the price.

Take another look at the nodes it covers. Samsung and Global Foundries were on most of those nodes where the price plateau starts. The only exceptions were the 7 nm nodes, which Global Foundries cancelled.

- Equipment amortization: Processes than used to have 2 or 3 year effective life are moving to 20 to 30 year life. Once much of the equipment is in place and paid for, the operation and maintenance costs start to dominate.

That doesn't help as much as you think. R&D + equipment has to be paid for over relatively short period of time. Having a long tail might be good for the fab's finances, but most of the datacenters, phones, and PCs run on new nodes and it doesn't really matter if those nodes become cheaper as they mature and are replaced by newer ones.

BTW, where did you get the idea that nodes used to have only a 2 or 3 year life? I doubt that's ever been true.

This goes across the supply chain to materials and mask generation as well.

I doubt masks are really getting cheaper, if that's what you're implying. Worse, each new node is generally using more masks. The main counterexample is when Intel went from DUV (Intel 7) to EUV (intel 4), where they were able to reduce mask count, slightly. Yet, the EUV masks are higher-density and almost certainly more expensive per-mask. The main benefit of fewer masks per wafer is just in production time/throughput.

 

[George³]

You don't have to use electrons though, they do now because it's the cheapest way to do it but they could use photons in the future (optical computing) , or a range of other things.

I suppose you read somewhere that photons are smaller than electrons and hence the ingenious conclusion that they can be worked with like this, as if we were continuing with decreasing size lithography?

 

[syadnom]

Should say 'at intel'.

If you include power use in the calculation, then the arm ecosystem has taken the baton.

Primarily Qualcomm proved ARM could perform well, they didn't push Moore's Law with anything but the laid the groundwork.

Now Apple's M1,2,3 series are keeping Moore's Law alive with performance-per-watt and to some degree raw performance.

And Qualcomm is now doing everything they can to have an answer to Apple's arm chip so I expect them to be matching intel's mainline performance in a generation or two.

It should be pointed out that Moore's law says 'about' 18 months, it's fuzzy. And the context was in personal computers. That means that even if we do invent optical computing or compact quantum computers etc they wont really 'count' for moore's law until you can put it in whatever personal computing device you're using.

 

[thestryker]

BTW, where did you get the idea that nodes used to have only a 2 or 3 year life? I doubt that's ever been true.

Intel's 45nm was very short lived but I think that is the only modern exception. I don't have much knowledge of anything before 90nm, but 90nm and 65nm were used for a pretty long time and 65nm was used for chipsets long after CPU retirement as was 32nm despite being very short lived as a leading node. 22nm will probably be used forever and 14nm is being used for chipsets now.

The main counterexample is when Intel went from DUV (Intel 7) to EUV (intel 4), where they were able to reduce mask count, slightly.

From what I've read it was a pretty significant cut, but this is the only example I'm aware of and this is just because of Intel going way too far with 10nm/Intel 7. I cannot imagine this type of circumstance happening again for anyone.

 

[bit_user]

It should be pointed out that Moore's law says 'about' 18 months, it's fuzzy. And the context was in personal computers.

Might want to fact-check yourself, before fact-checking the article.

"The observation is named after Gordon Moore, the co-founder of Fairchild Semiconductor and Intel (and former CEO of the latter), who in 1965 posited a doubling every year in the number of components per integrated circuit,[a] and projected this rate of growth would continue for at least another decade. In 1975, looking forward to the next decade, he revised the forecast to doubling every two years,"
...
"The doubling period is often misquoted as 18 months because of a separate prediction by Moore's colleague, Intel executive David House. In 1975, House noted that Moore's revised law of doubling transistor count every 2 years in turn implied that computer chip performance would roughly double every 18 months (with no increase in power consumption)."

https://en.wikipedia.org/wiki/Moore's_law
​

It should further be noted that PCs didn't exist in 1965 or 1975.

That means that even if we do invent optical computing

Optical computing has existed for a while. It just hasn't managed to surpass semiconductors. Its strengths have nothing to do with the relative size of electrons vs. photons, as far as I'm aware.

https://en.wikipedia.org/wiki/Optical_computing
​

 

[usertests]

There are plans to make at least 1000-layer NAND. Let's see 1000-layer CPUs.

I doubt masks are really getting cheaper, if that's what you're implying. Worse, each new node is generally using more masks. The main counterexample is when Intel went from DUV (Intel 7) to EUV (intel 4), where they were able to reduce mask count, slightly. Yet, the EUV masks are higher-density and almost certainly more expensive per-mask. The main benefit of fewer masks per wafer is just in production time/throughput.

High-NA EUV could help, despite also being expensive:

https://www.tomshardware.com/pc-com...en-process-nodes-could-cost-dollar400-million

 

[bit_user]

There are plans to make at least 1000-layer NAND. Let's see 1000-layer CPUs.

According to Jim Keller, die-stacking is (no longer) really applicable to CPUs, due to thermal density. Plus, with die stacking, costs should scale linear to the height of the stack, because you still have to fabricate the die in each layer.

View: https://www.youtube.com/watch?v=o70yKYWgtVI

​

Even if you're just talking about embedding multiple layers of logic within a single die, I think the thermal density issue still rears up.

High-NA EUV could help, despite also being expensive:

Yes, except it appears to be experiencing low yield. Also, it's purported to require a lot of new tooling, which sounds like its introduction could still take a while and come at rather high initial cost.

 

[usertests]

According to Jim Keller, die-stacking is (no longer) really applicable to CPUs, due to thermal density. Plus, with die stacking, costs should scale linear to the height of the stack, because you still have to fabricate the die in each layer.

3D in some form is the way forward, starting with moving gigabytes of memory into the CPU.

I know they are looking into ways to solve the thermal density problem, such as nanoscale cooling channels permeating the layers. If the industry stretches out these final planar nodes, there's probably another decade to figure out what to do.

While linear cost increases are not desirable, they can be tolerable for some customers who need whatever better-than-linear performance or efficiency increases may be possible from stacking up. Kind of like how Cerebras Wafer Scale Engine is a viable product at $2-10 million each.

 

[vehekos]

The only way to keep Moore's law going indefinitely is multivalued logic.
Hardware cannot more be binary. More should be done with the same atoms, since is not possible to get more atoms.

 

[kjfatl]

Take another look at the nodes it covers. Samsung and Global Foundries were on most of those nodes where the price plateau starts. The only exceptions were the 7 nm nodes, which Global Foundries cancelled.


That doesn't help as much as you think. R&D + equipment has to be paid for over relatively short period of time. Having a long tail might be good for the fab's finances, but most of the datacenters, phones, and PCs run on new nodes and it doesn't really matter if those nodes become cheaper as they mature and are replaced by newer ones.

BTW, where did you get the idea that nodes used to have only a 2 or 3 year life? I doubt that's ever been true.


I doubt masks are really getting cheaper, if that's what you're implying. Worse, each new node is generally using more masks. The main counterexample is when Intel went from DUV (Intel 7) to EUV (intel 4), where they were able to reduce mask count, slightly. Yet, the EUV masks are higher-density and almost certainly more expensive per-mask. The main benefit of fewer masks per wafer is just in production time/throughput.

 

[kjfatl]

When I started doing ASIC design back in the 1980's, it was not uncommon for small fabs to have only 2 active processes, something like 6micron and 4 micron. When the fab was ready to go to the next process, 3 micron, most of the equipment for the older 6 micron process would be sold and new equipment was installed to support the new process. If you wanted to build additional 6 micron parts, you were forced to move the masks to another fab, or spend the $15K to make a new mask set for a newer process. In those days, we were forced to move to a new process every 2 or 3 years or do last time buys. Those days are long gone for most logic designs.

For newer products, Intel and others have moved to using chiplets. In many modern designs, less than 10% of the design is required to run at the highest speeds. Than means for even high end parts, the bulk of the silicon can use older, cheaper processes.

Yes, masks are getting more expensive and more are needed in most cases, unless multi-patterning can be eliminated. Still, the companies making masks will likely increase their skillsets and the cost to generate masks for the older processes will drop.

Some of the older nodes will be reduced in cost when EUV added, eliminating the need for multi-patterning. This will be an incentive for fabs such as Intel and TSMC to hold onto the early EUV equipment much longer than with previous generations of equipment.

 

[bit_user]

The only way to keep Moore's law going indefinitely is multivalued logic.
Hardware cannot more be binary. More should be done with the same atoms, since is not possible to get more atoms.

Just remember that the size & complexity of the gates can't increase as fast as the number of bits you're processing at once.

Also, keep in mind that circuits are currently tuned to use the minimum voltage levels and maximum frequencies possible, for processing only 2 states. Once you increase the number of states per wire, they'll probably have to back off frequency and increase voltage to represent them stably.

Therefore, I'm not convinced it's a win. You might be right, but I think it'll take much more than a thought experiment to convince me. ...not to mention all the needed reworking of software that currently depends on binary representations.

 

[bit_user]

I'm convinced we're headed for some fundamental rethinking of the sequential ISA model that's dominated computing until now. If you compare the energy-efficiency of VLIW DSP cores with local SRAM to that of huge out-of-order cores with multi-level cache hierarchies, it's clear that the simplistic sequential execution model of modern CPUs is too wasteful.

The hardware is burning too much energy & die area repeatedly proving things at runtime that are often knowable at compile-time. Meanwhile, the software has only indirect ways of harnessing the hardware's power to make guesses, based on detecting patterns in runtime behavior.

I'm not saying VLIW is the answer, but we need to think of better ways to strike a balance between the two extremes.

 

[bit_user]

In many modern designs, less than 10% of the design is required to run at the highest speeds.

Let's restrict our discussion to modern CPUs and GPUs. In those instances, I think it's a lot more than 10%. If you look at the relative sizes of the tiles in Meteor Lake, that should be pretty clear. Even though not everything in the CPU tile needs to run at top speed, everything on that tile at least needs to be near logic that's sensitive to frequency or density.

Also, Meteor Lake's GPU tile was rumored to be targeted at TSMC N3, but dropped back to N5 for some reason. So, that'd be two fairly substantial tiles on the most advanced nodes.

I think AMD already showed one way forward, which is to move L3 cache to a stacked die on an older node. How much more can you move? Not much, I fear. And don't forget that they stacked SRAM on SRAM. They couldn't stack SRAM on logic for thermal reasons.

the companies making masks will likely increase their skillsets and the cost to generate masks for the older processes will drop.

I'm sure that's already been happening. It should be baked into the cost curves, already. It's probably one of the reasons costs decrease on nodes as they mature.

 

[George³]

While linear cost increases are not desirable, they can be tolerable for some customers who need whatever better-than-linear performance

Yes, but this is not description of average home user. I think that prices of lowering nodes will make production unbearably dear, not too many years from now. Moreover, it will not be able to "ripen" to prices that will be bearable even after maximum refinement.

 

[vehekos]

Therefore, I'm not convinced it's a win. You might be right, but I think it'll take much more than a thought experiment to convince me. ...not to mention all the needed reworking of software that currently depends on binary representations.

Multivalued transistors are not a thought experiment
Multivalued transistors demonstrated on wafer-scale
High-performance multivalued logic circuits based on optically tunable antiambipolar transistors†

A 4 state transistor can emulate 2 binary transistors, so it could be used to implement 2 CPU in the same atoms, running 2 different programs. It would not demand designing new software.

SIMD hardware could double. L1 Cache could double.

Chip size could be reduced quadratically. Yields would increase exponentially.

 

[KraakBal]

Stfu and execute. Please be less boring in 2024!