There is a mistake in the article - Haswell EP is >far< from the QS phase.
The way it goes for Xeon is this: pre-silicon -> ES0 -> ES1 -> ES2 -> QS -> Production
QS is the last step before production, and for Xeon EP CPUs it typically comes ~4-6 months before the launch date. For EX Xeons testing phases are considerably longer due to RAS features.
Also, Ivy Bridge EP comes with different die variants (high core count, etc.) so 4960X is not castrated 12-core 269x v2, but it comes from lower-core count dies.
I do not know the reason why Intel does not put more cores on consumer i7, but I suppose it has something to do with the fact that in the consumer space there are simply no "killer apps" for more than 6 cores and the single-core frequency often means much more to the consumer due to crappy consumer software/games not optimized properly to use multiple cores.
Business factors probably play a role too but I guess not as much as with the SNB-EP (yields should not be the issue with Ivy Bridge EP due to different dies with low core count, as it was the case with SNB-EP where 3930/3960x/3970x were originally 8-core dies with 2 cores fused off). Probably the lack of proper competition from AMD does not help either.
Another thing to think about is overclocking - I suppose significant proportion of consumers for the HEDT Core i7 segment are overclocking. While the TDP of 12-core Xeon is still 130W, this is so only because the clock is kept comparatively low compared to i7. If Intel would allow voltage manipulation and overclocking of the 12-core part, it is quite easy to blow the TDP off the chart (probably well over 500W) by irresponsible overclocking (say, pushing the VCC to 1.45v and multiplier to 48x+) - this would probably damage most motherboards, and also it would require mandatory requirements to be much more expensive in terms of voltage regulation circuitry. Even with all precautions, there would be much more fried motherboards and this is bad for marketing.