News Intel's Meteor Lake CPUs for Desktops Incoming, but There's a Catch

[Admin]

Intel's Meteor Lake-S for desktops will reportedly only exist in up to Core i5 models. That's what the latest information reveals.

Intel's Meteor Lake CPUs for Desktops Incoming, but There's a Catch : Read more

 

[mac_angel]

their naming scheme is pretty confusing, and pretty sure it's meant to be.
I'm also kinda wondering about cost of changing manufacturing techniques so often. At the beginning of a new node/technology, the quality numbers aren't that high. By the time they get going with quality results in higher percentages, they are changing to a different manufacturing node/technology.

 

[KyaraM]

Heh, interesting. So the rumors of Meteor Lake-S cancelation were only half true.I wonder if this is done as a first test run, to see how the tech will fare irl?

 

[bit_user]

I'm having deja vu of the whole Ice Lake vs. Rocket Lake situation.

Sounds like Intel 4 doesn't clock very high or like high power, similar to Intel's early and mid 10 nm nodes.

 

[bit_user]

Heh, interesting. So the rumors of Meteor Lake-S cancelation were only half true.I wonder if this is done as a first test run, to see how the tech will fare irl?

The back-and-forth aspect of the rumors is interesting. I imagine Intel got push back from its board and system partners, who invested significant resources in preparing LGA1851 products for launch in 2023, and otherwise would have no way to recoup that investment until 2024.

That's not to say they won't be competitive in their respective performance segments, but it just seems like a lot of effort to address only that slice of the market.

 

[TerryLaze]

Or since raptor lake is only raptor lake from i5 upwards, they will now replace the 13th gen alder lake CPUs with meteor lake and will keep milking money from i5 and up raptor lake that they will maybe give a refresh.
Then they will get new i5 and up with arrow lake while probably keeping the i5 and below at an meteor refresh for a few more months.

 

[bit_user]

they will now replace the 13th gen alder lake CPUs with meteor lake

That's a good point. It resolves the current situation with the Alder Lake -> Gen 13 rebadges.

 

[kjfatl]

I wonder if the issue is something more mundane. Fab capacity at particular nodes.

 

[bit_user]

I wonder if the issue is something more mundane. Fab capacity at particular nodes.

Well, Sierra Forest and Granite Rapids are both slated to use Intel 3. So, that would align with either a yield or capacity problem with Intel 4, as well as frequency. Or, it could just mean that their launch window naturally aligns with Intel 3. As I'm not aware of any other products announced on Intel 4, I can't really find an indication one way or another.

I would point out that only the CPU tile is supposed to be Intel 4. So, that shouldn't be as demanding on fab capacity as prior CPUs. All that really tells us is that yield and fab capacity are less likely to be limiting factors. I'm not sure we'll really know, unless they start cranking out a bunch of 3rd party server CPUs on Intel 4.

 

[SiliconFly]

I'm having deja vu of the whole Ice Lake vs. Rocket Lake situation.

Sounds like Intel 4 doesn't clock very high or like high power, similar to Intel's early and mid 10 nm nodes.

Actually, it points to two things:

(1) Doesn't clock well.
(2) Keeping the cpu tile small due to yield issues

 

[bit_user]

Actually, it points to two things:

...
(2) Keeping the cpu tile small due to yield issues

There are other reasons to use tiles:

• The optimal process node for CPU and GPU aren't the same. I don't know too much about this, but I've seen it mentioned several times, on different sites.
• I/O and SRAM benefit less from smaller nodes, so putting cache & I/O on an older node is more economical without much downside. AMD even uses TSMC N7 for the 3D cache chiplets in its Ryzen 7000X3D models.
• Limits requirements on production capacity of newest node, which might still be in its ramp-up phase.
• Cost savings, as newer nodes are now always more expensive (i.e. not derivative nodes, but speaking of meaningfully different nodes).

A further possibility is that production lines that would've been built for Intel 4 are instead being setup for Intel 3, which is a derivative node and thus can probably use most of the same equipment. This could lead to a faster ramp-up for it, and might be necessary for their aggressive timeline for Sierra Forest and Granite Rapids.

 

[SiliconFly]

There are other reasons to use tiles:

• The optimal process node for CPU and GPU aren't the same. I don't know too much about this, but I've seen it mentioned several times, on different sites.
• I/O and SRAM benefit less from smaller nodes, so putting cache & I/O on an older node is more economical without much downside. AMD even uses TSMC N7 for the 3D cache chiplets in its Ryzen 7000X3D models.
• Limits requirements on production capacity of newest node, which might still be in its ramp-up phase.
• Cost savings, as newer nodes are now always more expensive (i.e. not derivative nodes, but speaking of meaningfully different nodes).

A further possibility is that production lines that would've been built for Intel 4 are instead being setup for Intel 3, which is a derivative node and thus can probably use most of the same equipment. This could lead to a faster ramp-up for it, and might be necessary for their aggressive timeline for Sierra Forest and Granite Rapids.

Makes me wonder why Intel chose to keep MTL cpu tile small when they could have had 8P+16E or even 8P+32E on Intel 4. Just wondering what happened?

Either yield issue or severe clock speed regression? They've had the same issue before many times! Just saying.

 

[TerryLaze]

Makes me wonder why Intel chose to keep MTL cpu tile small when they could have had 8P+16E or even 8P+32E on Intel 4. Just wondering what happened?

Either yield issue or severe clock speed regression? They've had the same issue before many times! Just saying.

We already saw a 6p+8e cores tile, so they could make a CPU with two of them for 12p + 16e cores which will be enough to be a good bit faster than the 8+16 13900.

 

[bit_user]

Makes me wonder why Intel chose to keep MTL cpu tile small when they could have had 8P+16E or even 8P+32E on Intel 4. Just wondering what happened?

First, on the topic of 6P, I think Intel is shifting towards a higher ratio of E to P cores. The whole point of P cores is for lightly-threaded jobs. You probably don't have get above 6 P cores before it makes more sense to start shift work to E-cores. Some future client CPUs have been rumored to have as many as 32 E-cores.

On the topic of small die vs. big die, perhaps they had 2 tile sizes planned: 6+8 and 10+24 (just guessing) and the larger one got canceled for reasons similar to Ice Lake vs. Whiskey Lake? For a high-end laptop, people are going to want strong single-threaded performance, and if they couldn't clock Meteor Lake high enough to beat the top-spec Raptor Lake CPUs, then its fate was the same as the > 4-core Ice Lake models.

Either yield issue or severe clock speed regression? They've had the same issue before many times! Just saying.

Their fix for that seems to be called Intel 3. Then again, Arrow Lake is supposed skip that and go straight to 20A.

We already saw a 6p+8e cores tile, so they could make a CPU with two of them for 12p + 16e cores which will be enough to be a good bit faster than the 8+16 13900.

Could be. In something like a laptop, however, I think there's a stronger efficiency argument for trying to keep the CPU tile monolithic.

 

[SiliconFly]

We already saw a 6p+8e cores tile, so they could make a CPU with two of them for 12p + 16e cores which will be enough to be a good bit faster than the 8+16 13900.

Two tiles may exceed the laptop power envelope. 🙁

 

[TerryLaze]

Two tiles may exceed the laptop power envelope. 🙁

That makes no sense at all unless there is a certain amount of power a tile has to have just to function...
It might constrain the cores too much and make them run too low a clock to make sense as a product but that would be a different thing.

 

[bit_user]

That makes no sense at all unless there is a certain amount of power a tile has to have just to function...

Unless you power it down, the cache needs to handle snoops.

I don't expect CPU 2 tiles would exceed the envelope for a higher-powered laptop, but I think single-threaded performance won't be competitive for that market segment. If true, that would pragmatically restrict it to just one small CPU tile.

 

[TerryLaze]

Unless you power it down, the cache needs to handle snoops.

I don't expect CPU 2 tiles would exceed the envelope for a higher-powered laptop, but I think single-threaded performance won't be competitive for that market segment. If true, that would pragmatically restrict it to just one small CPU tile.

Single threaded is the speed you have if only one single thread is running, that will always be high since you will only power a single core.

Divide the multicore score of the 7950x by amount of threads and compare it to the single thread score to see that the per core speed (which I guess is what you mean) doesn't matter much.

 

[bit_user]

Single threaded is the speed you have if only one single thread is running, that will always be high since you will only power a single core.

Again, look at Ice Lake. It had higher IPC, but not enough to offset the drop in clockspeed relative to Coffee Lake. That restricted it to the low-power laptop market. That also meant only 4 cores.

 

[SiliconFly]

That makes no sense at all unless there is a certain amount of power a tile has to have just to function...
It might constrain the cores too much and make them run too low a clock to make sense as a product but that would be a different thing.

A core requires a certain amount of power (TDP) to run at maximum performance. It's fixed during manufacturing and cannot be varied at runtime. If a laptop is designed to supply 45W to a cpu, then a MTL CPU tile with 6P+8E rated at 45W TDP is all it can handle. Anymore, it'll falter.

Conversely, if we try to stick 2 tCPU tiles rated at 45W each into a single 45W cpu package, then both tiles will suffer from power shortages. They won't clock well & might even lose sync with the ring bus, memory controller, io controllers, etc. Not a good scenario.